US4922493A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error detection and correction circuit
Assignee: Motorola Solutions Japan Ltd
•
Filing: 1988-08-15
•
Granted: 1990-05-01
•
Expires: 2008-08-15
Abstract
Abstract An overload circuit detects input signals that are too high or too low in amplitude and generates a holding signal of a predetermined duration. The holding signal is applied to a data selector which normally passes the input signal to a shift register/majority gate but switches to supply the output of the majority gate to the shift register when a holding signal is present. Thus, the output is maintained constant during the predetermined durations when a holding singnal is present.
Inventors
- 👤 Kiyoshi Kase
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:28
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/068; G; G06; G06K; G06K7/00; G06K7/0008; G06K7/0013; G06K7/0086; H03; H03K; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
150 words
An error detection and correction circuit comprising an overload detector which detects when an input signal level goes beyond a predetermined range of change and develops an overload signal, an error correction period setting part connected to receive the overload signal and providing an error correction signal for a specified period after the overload signal is provided from the overload detector, a data memory which sequentially stores a predetermined amount of input signal data, a majority gate connected to said data memory for developing a majority signal determined by the majority rule of the predetermined amount of data stored in said data memory, and a switch circuit connected to said data memory, said correction period setting part, and said majority gate for providing an output of said majority gate in place of the signal corresponding to the input signal data to said data memory while the error correction signal exists.
Claim 2
Dependent Claim
150 words
An error detection and correction circuit comprising an overload detector which detects when an input signal level goes beyond a predetermined range of change and develops an overload signal, an error correction period setting part connected to receive the overload signal and providing an error correction signal for a specified period after the overload signal is provided from the overload detector, a data memory which sequentially stores a predetermined amount of input signal data, a majority gate connected to said data memory for developing a majority signal determined by the majority rule of the predetermined amount of data stored in said data memory, and a switch circuit connected to said data memory, said correction period setting part, and said majority gate for providing an output of said majority gate in place of the signal corresponding to the input signal data to said data memory while the error correction signal exists.
Claim 3
Dependent Claim
82 words
An error detection and correction circuit according to claim 1, wherein the overload detector comprises a positive direction overload detecting circuit which detects when the input signal level goes beyond the predetermined range of change in the positive direction, a negative direction overload detecting circuit which detects when the input signal level goes beyond the predetermined range in the negative direction, and an OR gate which carries out the OR calculations of outputs of these positive and negative direction overload detecting circuits.
Claim 4
Dependent Claim
35 words
An error detection and correction circuit according to claim 1, wherein the error correction period setting part is formed by a predetermined number of stages of shift register to which the overload signal is fed.
Claim 5
Dependent Claim
25 words
An error detection and correction circuit according to claim 1, wherein the data memory is formed by a predetermined number of stages of shift register.
References Cited (Backward Citations)
US3386079A
Cited
US3568147A
Cited
US3688039A
Cited
US3697776A
Cited
US4224689A
Cited
US4519001A
Cited
US4639920A
Cited
US4686676A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-30 | 1993-10-30 | 1994-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-30 | 1997-10-30 | 1998-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-30 | 2001-10-30 | 2002-05-01 | $7700.00 | Window Closed / Lapsed |