CMOS voltage multiplier

Claim 1

A wholly integrated, multistage, CMOS voltage multiplier comprising a plurality of diodes or equivalent integrated structures functionally connected in series between a supply terminal and an output terminal through which a current may be delivered at a voltage having an absolute value higher than the absolute value of a supply voltage applied to said supply terminal and at least a stage output capacitor connected between each intermediate node between any two diodes of said series of diodes and between said output terminal and alternately a first and a second rail to which are respectively applied two square-wave switching signals, in phase opposition to each other and having a high absolute value which is substantially equal to the absolute value of said supply voltage and a substantially nil low absolute value, wherein at least one of said diode equivalent integrated structures comprises a first enhancement-type CMOS transistor of a first type of polarity, having a source and a drain functionally connected respectively to a first intermediate node and to a successive second intermediate node of said series or to said output terminal, a body electrically short-circuited to said drain and a gate which is coupled through a coupling capacitor to the one of said first and second rails to which said stage output capacitor, connected to said successive second intermediate node of the series or to said output terminal is connected; a second enhancement-type CMOS transistor, having the same polarity and a threshold voltage identical to said first enhancement-type CMOS transistor and having a drain and a body connected in common to said successive second intermediate node of the series and a gate and a source connected in common to the gate of said first CMOS transistor; said coupling capacitor charging through said second transistor, for determining the cut-off of said first transistor during a conducting phase of the latter, at a maximum voltage having an absolute value lower than the absolute value of the voltage of said successive intermediate node by a quantity equal to the absolute value of the threshold voltage of said second transistor, and allowing electric charge transfer from said first intermediate node to said successive second intermediate node or to said output terminal through said first transistor under a null threshold condition.