Circuit for separating composite color television signal into luminance signal and chrominance signal

Claim 2

A circuit for separating a luminance signal and a chrominance signal from a composite color television signal supplied to an input terminal and outputting the luminance and chrominance signals, comprising: first delay means for delaying the composite color television signal supplied to said input terminal by one horizontal line period; first extracting means for extracting frequency components in the vicinity of a color subcarrier frequency from the composite color television signal supplied to said input terminal; second extracting means for extracting frequency components in the vicinity of the color subcarrier frequency from an output signal of said first delay means; first waveform selecting mean connected to receive a first signal obtained by inverting one of the output signals of said first and second extracting means and a second signal corresponding to another output signal of said first and second extracting means, for extracting only those components of the first and second signals which have the same waveform at the same time; second delay means for delaying an output signal of said first waveform selecting means by one horizontal line time; second waveform selecting means connected to receive a third signal obtained by inverting one of the output signals of said first waveform selecting means and said second delay means and a fourth signal corresponding to another output signal of said first waveform selecting means and said second delay means, for extracting only those components of the third and fourth signals which have the same waveform at the same time; adder means for adding the third and fourth signals; first signal synthesizing means for performing subtraction between the output signal of said second waveform selecting means and the output signal of said adder means to provide the chrominance signal; and second signal synthesizing means for adding the output signal of said first signal synthesizing means and the output signal of said first delay means to provide the luminance signal.

Claim 3

The circuit according to claim 1, wherein said first waveform selecting means includes: first inverting means for inverting one of the output signals of said first and second extracting means to provide the first signal; and first intermediate value circuit means connected to receive the first signal and the second signal for outputting components of the first and second signals which become the same waveform simultaneously.

Claim 4

The circuit according to claim 2, wherein said first intermediate value circuit means includes: a first input terminal for receiving the first signal; a second input terminal for receiving the second signal; a control input terminal for receiving a control signal whose alternating current component is zero; a first minimum value circuit connected to receive the first signal supplied to said first input terminal and the control signal supplied to said control terminal for selectively outputting a lower level of the first signal and the control signal; a second minimum value circuit connected to receive the second signal supplied to said second input terminal and the control signal supplied to said control terminal for selectively outputting a lower level of the second signal and the control signal; a third minimum value circuit connected to receive the first signal supplied to said first input terminal and the second signal supplied to said second input terminal for selectively outputting a lower level of the first and second signals; and a maximum value circuit connected to receive output signals of said first through third minimum value circuits for selectively outputting the highest level of the output signals.

Claim 5

The circuit according to claim 2, wherein said first intermediate value circuit means includes: a first input terminal for receiving the first signal; a second input terminal for receiving the second signal; a control input terminal for receiving a control signal whose alternating current component is zero; a first maximum value circuit connected to receive the first signal supplied to said first input terminal and the control signal supplied to said control terminal for selectively outputting a higher level of the first signal and the control signal; a second maximum value circuit connected to receive the second signal supplied to said second input terminal and the control signal supplied to said control terminal for selectively outputting a higher level of the second signal and the control signal; a third maximum value circuit connected to receive the first signal supplied to said first input terminal and the second signal supplied to said second input terminal for selectively outputting a higher level of the first and second signals; and a minimum value circuit connected to receive output signals of said first through third maximum value circuits for selectively outputting the lowest level of the output signals.

Claim 6

The circuit according to claim 2, wherein said second waveform selecting means includes: second inverting means for inverting one of the output signals of said first waveform selecting means and said second delay means to provide the third signal; and second intermediate value circuit means connected to receive the third signal and the fourth signal for outputting components of the third and fourth signals which become the same waveform simultaneously.

Claim 7

The circuit according to claim 5, wherein said second intermediate value circuit means includes: a first input terminal for receiving the third signal; a second input terminal for receiving the fourth signal; a control input terminal for receiving a control signal whose alternating current component is zero; a first minimum value circuit connected to receive the third signal supplied to said first input terminal and the control signal supplied to said control terminal for selectively outputting a lower level of the third signal and the control signal; a second minimum value circuit connected to receive the fourth signal supplied to said second input terminal and the control signal supplied to said control terminal for selectively outputting a lower level of the fourth signal and the control signal; a third minimum value circuit connected to receive the third signal supplied to said first input terminal and the fourth signal supplied to said second input terminal for selectively outputting a lower level of the third and fourth signals; and a maximum value circuit connected to receive output signals of said first through third minimum value circuits for selectively outputting the highest level of the output signals.

Claim 8

The circuit according to claim 5, wherein said second intermediate value circuit means includes: a first input terminal for receiving the third signal; a second input terminal for receiving the fourth signal; a control input terminal for receiving a control signal whose alternating current component is zero; a first maximum value circuit connected to receive the third signal supplied to said first input terminal and the control signal supplied to said control terminal for selectively outputting a higher level of the third signal and the control signal; a second maximum value circuit connected to receive the fourth signal supplied to said second input terminal and the control signal supplied to said control terminal for selectively outputting a higher level of the fourth signal and the control signal; a third maximum value circuit connected to receive the third signal supplied to said first input terminal and the fourth signal supplied to said second input terminal for selectively outputting a higher level of the third and fourth signals; and a minimum value circuit connected to receive output signals of said first through third maximum value circuits for selectively outputting the lowest level of the output signals.

Claim 9

The circuit according to claim 1, wherein said first signal synthesizing means includes: inverting means for inverting the output signal of said second waveform selecting means; and adder circuit means for adding an output signal of said inverting means to the output signal of said adder means.

Claim 10

A circuit for separating a luminance signal and a chrominance signal from a composite color television signal supplied to an input terminal and outputting the luminance and chrominance signals, comprising: first delay means for delaying the composite color television signal supplied to said input terminal by one horizontal line period; first extracting means for extracting frequency components in the vicinity of a color subcarrier frequency from the composite color television signal supplied to said input terminal to provide a first signal; second extracting means for extracting frequency components in the vicinity of the color subcarrier frequency from an output signal of said first delay means to provide a second signal; first waveform selecting means connected to receive the first and second signals from said first and second extracting means, for extracting only these components of the first and second signals which have the same waveform at the same time, providing a third signal; second delay means for delaying the third signal from said first waveform selecting means by one horizontal line time, to provide a fourth signal; second waveform selecting means connected to receive the third signal from said first waveform selecting means and the fourth signal from said second delay means for extracting only those components of the third and fourth signals which have the same waveform at the same time; adder means for adding the third and fourth signals; first subtracting means for performing subtraction between output signals of said second waveform selecting means and said adder means; second subtracting means for performing subtraction between the output signal of said first delay means and the output signal of said second extracting means; first signal synthesizing means for performing subtraction between the output signal of said first subtracting means and the second signal from said second extracting means, to provide the chrominance signal; and second signal synthesizing means for adding the output signal of said first subtracting means and an output signal of said second subtracting means, to provide the luminance signal.

Claim 11

A circuit for separating a luminance signal and a chrominance signal from a composite color television signal supplied to an input terminal and outputting the luminance and chrominance signals, comprising: first delay means for delaying the composite color television signal supplied to said input terminal by one horizontal line period; first extracting means for extracting frequency components in the vicinity of a color subcarrier frequency from the composite color television signal supplied to said input terminal to provide a first signal; second extracting means for extracting frequency components in the vicinity of the color subcarrier frequency from an output signal of said first delay means to provide a second signal; first waveform selecting means connected to receive the first and second signals from said first and second extracting means, for extracting only these components of the first and second signals which have the same waveform at the same time, providing a third signal; second delay means for delaying the third signal from said first waveform selecting means by one horizontal line time, to provide a fourth signal; second waveform selecting means connected to receive the third signal from said first waveform selecting means and the fourth signal from said second delay means for extracting only those components of the third and fourth signals which have the same waveform at the same time; adder means for adding the third and fourth signals; first subtracting means for performing subtraction between output signals of said second waveform selecting means and said adder means; second subtracting means for performing subtraction between the output signal of said first delay means and the output signal of said second extracting means; first signal synthesizing means for performing subtraction between the output signal of said first subtracting means and the second signal from said second extracting means, to provide the chrominance signal; and second signal synthesizing means for adding the output signal of said first subtracting means and an output signal of said second subtracting means, to provide the luminance signal.

Claim 12

The circuit according to claim 9, wherein said first waveform selecting means includes: a first input terminal for receiving the first signal; a second input terminal for receiving the second signal; a control input terminal for receiving a control signal whose alternating current component is zero; a first minimum value circuit connected to receive the first signal supplied to said first input terminal and the control signal supplied to said control terminal for selectively outputting a lower level of the first signal and the control signal; a second minimum value circuit connected to receive the second signal supplied to said second input terminal and the control signal supplied to said control terminal for selectively outputting a lower level of the second signal and the control signal; a third minimum value circuit connected to receive the first signal supplied to said first input terminal and the second signal supplied to said second input terminal for selectively outputting a lower level of the first and second signals; and a maximum value circuit connected to receive output signals of said first through third minimum value circuits for selectively outputting the highest level of the output signals.

Claim 13

The circuit according to claim 9, wherein said first waveform selecting means includes: a first input terminal for receiving the first signal; a second input terminal for receiving the second signal; a control input terminal for receiving a control signal whose alternating current component is zero; a first maximum value circuit connected to receive the first signal supplied to said first input terminal and the control signal supplied to said control terminal for selectively outputting a higher level of the first signal and the control signal; a second maximum value circuit connected to receive the second signal supplied to said second input terminal and the control signal supplied to said control terminal for selectively outputting a higher level of the second signal and the control signal; a third maximum value circuit connected to receive the first signal supplied to said first input terminal and the second signal supplied to said second input terminal for selectively outputting a higher level of the first and second signals; and a minimum value circuit connected to receive output signals of said first through third maximum value circuits for selectively outputting the lowest level of the output signals.

Claim 14

The circuit according to claim 9, wherein said second intermediate value circuit means includes: a first input terminal for receiving the third signal; a second input terminal for receiving the fourth signal; a control input terminal for receiving a control signal whose alternating current component is zero; a first minimum value circuit connected to receive the third signal supplied to said first input terminal and the control signal supplied to said control terminal for selectively outputting a lower level of the third signal and the control signal; a second minimum value circuit connected to receive the fourth signal supplied to said second input terminal and the control signal supplied to said control terminal for selectively outputting a lower level of the fourth signal and the control signal; a third minimum value circuit connected to receive the third signal supplied to said first input terminal and the fourth signal supplied to said second input terminal for selectively outputting a lower level of the third and fourth signals; and a maximum value circuit connected to receive output signals of said first through third minimum value circuits for selectively outputting the highest level of the output signals.

Claim 15

The circuit according to claim 9, wherein said second intermediate value circuit means includes: a first input terminal for receiving the third signal; a second input terminal for receiving the fourth signal; a control input terminal for receiving a control signal whose alternating current component is zero; a first maximum value circuit connected to receive the third signal supplied to said first input terminal and the control signal supplied to said control terminal for selectively outputting a higher level of the third signal and the control signal; a second maximum value circuit connected to receive the fourth signal supplied to said second input terminal and the control signal supplied to said control terminal for selectively outputting a higher level of the fourth signal and the control signal; a third maximum value circuit connected to receive the third signal supplied to said first input terminal and the fourth signal supplied to said second input terminal for selectively outputting a higher level of the third and fourth signals; and a minimum value circuit connected to receive output signals of said first through third maximum value circuits for selectively outputting the lowest level of the output signals.

Claim 16

The circuit according to claim 9, wherein said first subtracting means includes: inverting means for inverting the output signal of said second waveform selecting means; and adder circuit means for adding an output signal of said inverting means and the output signal of said adder means.

Claim 17

The circuit according to claim 9, wherein said second subtracting means includes: inverting means for inverting the second signal of said second extracting means; and adder circuit means for adding an output signal of said inverting means to the output signal of said first delay means.

Claim 18

The circuit according to claim 9, wherein said first signal synthesizing means includes: inverting means for inverting the second signal from said second extracting means; and adder circuit means for adding an output signal of said inverting means to the output signal of said first subtracting means.