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US4918647A Expired / Lapsed US ⏱️ 0.0 years remaining

Programmable interface unit which generates dedicated control signals in response to a single control word

Assignee: Burr Brown Ltd
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Filing: 1986-08-04
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Granted: 1990-04-17
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Expires: 2006-08-04
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Abstract

Abstract A unit for providing an interface between analog input signals and a digital data processing system bus includes a plurality of sample-and-hold circuits coupled to the analog input signals, a multiplexer for selecting a particular sample-and-hold circuit, and an analog-to-digital converter for providing a digital signal related to the amplitude of a selected portion of the input signal. A control circuit provides control signals for controlling the operation of the sample-and-hold circuits, the multiplexer, and the analog-to-digital converter circuit. The control circuit can receive and store signals from the data processing system and use such signals to control the operation of the interface unit.

Inventors

  • 👤 Philip A. Downey

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 12:08
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/05

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 253 words
An enhancement to a digital signal processing system provided with a system bus, a data processing unit and a memory unit respectively coupled to the system bus for developing an interface control word and for applying the interface control word to the system bus, said digital signal processing system also provided with a control register, a control transfer bus (50) coupled between the system bus and the control register for causing the interface control word to be entered into the control register, a digitizer coupled to the system bus for transmitting digitized analog input signals, the digitizer comprising a sample-and-hold circuit electronically coupled to a multiplexer unit, that in turn is coupled to an analog-to-digital converter, said enhancement to said digital processing system comprising: (a) a first control line coupled between the control register and the sample-and-hold circuit for delivering a first control signal generated by said control register in response to the entered interface control word for determining the time duration for monitoring an analog input signal; (b) a second control line coupled between the control register and the multiplexer for delivering a second control signal generated by said control register in response to the entered interface control word for determining which analog input signal is monitored; and (c) a third control line coupled between the control register and the analog-to-digital converter for delivering a third control signal generated by said control register in response to the entered interface control word for determining when the analog-to-digital converter processes an analog input signal.
Claim 2
Dependent Claim 253 words
An enhancement to a digital signal processing system provided with a system bus, a data processing unit and a memory unit respectively coupled to the system bus for developing an interface control word and for applying the interface control word to the system bus, said digital signal processing system also provided with a control register, a control transfer bus (50) coupled between the system bus and the control register for causing the interface control word to be entered into the control register, a digitizer coupled to the system bus for transmitting digitized analog input signals, the digitizer comprising a sample-and-hold circuit electronically coupled to a multiplexer unit, that in turn is coupled to an analog-to-digital converter, said enhancement to said digital processing system comprising: (a) a first control line coupled between the control register and the sample-and-hold circuit for delivering a first control signal generated by said control register in response to the entered interface control word for determining the time duration for monitoring an analog input signal; (b) a second control line coupled between the control register and the multiplexer for delivering a second control signal generated by said control register in response to the entered interface control word for determining which analog input signal is monitored; and (c) a third control line coupled between the control register and the analog-to-digital converter for delivering a third control signal generated by said control register in response to the entered interface control word for determining when the analog-to-digital converter processes an analog input signal.
Claim 3
Dependent Claim 298 words
In a digital signal processing system that includes a data processing unit coupled to a system bus, a control transfer bus coupled between said system bus and a control register for causing an interface control word to be entered into said control register, a digitizer coupled to said system bus for transmitting a digitized analog input signal, said digitizer comprising a sample-and-hold circuit electronically coupled to a multiplexer unit that in turn is coupled to an analog-to-digital converter, a method of interfacing at least one analog signal source to the system bus, the method comprising the steps of: (a) providing a first control line coupled between the control register and the sample-and-hold circuit for delivering a first control signal for determining the time duration for monitoring an analog input signal; (b) providing a second control line coupled between the control register and the multiplexer for delivering a second control signal for determining which analog input signal is monitored; (c) providing a third control line coupled between the control register and the analog-to-digital converter for delivering a third control signal for determining when the analog-to-digital converter processes an analog input signal; (d) transferring the interface control word from the system bus to an input of said control register; (e) generating said first, second, and third control signals by said control register in response to said interface control word onto said first, second, and third control lines described in steps (a), (b) and (c) for determining the time duration for monitoring an analog input signal, determining which analog input signal is being monitored and determining when the analog-to-digital converter processes an analog input signal; (f) digitizing the analog signal during a digitizing time in response to the interface control word; and (g) coupling the digitized signal to the system bus.
Claim 4
Dependent Claim 298 words
In a digital signal processing system that includes a data processing unit coupled to a system bus, a control transfer bus coupled between said system bus and a control register for causing an interface control word to be entered into said control register, a digitizer coupled to said system bus for transmitting a digitized analog input signal, said digitizer comprising a sample-and-hold circuit electronically coupled to a multiplexer unit that in turn is coupled to an analog-to-digital converter, a method of interfacing at least one analog signal source to the system bus, the method comprising the steps of: (a) providing a first control line coupled between the control register and the sample-and-hold circuit for delivering a first control signal for determining the time duration for monitoring an analog input signal; (b) providing a second control line coupled between the control register and the multiplexer for delivering a second control signal for determining which analog input signal is monitored; (c) providing a third control line coupled between the control register and the analog-to-digital converter for delivering a third control signal for determining when the analog-to-digital converter processes an analog input signal; (d) transferring the interface control word from the system bus to an input of said control register; (e) generating said first, second, and third control signals by said control register in response to said interface control word onto said first, second, and third control lines described in steps (a), (b) and (c) for determining the time duration for monitoring an analog input signal, determining which analog input signal is being monitored and determining when the analog-to-digital converter processes an analog input signal; (f) digitizing the analog signal during a digitizing time in response to the interface control word; and (g) coupling the digitized signal to the system bus.

References Cited (Backward Citations)

US4145751A Cited
US4638451A Cited
US4548161A Cited
JPS6072001A Cited
US4611296A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-04-16 1993-10-16 1994-04-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-04-16 1997-10-16 1998-04-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-04-16 2001-10-16 2002-04-17 $7700.00 Window Closed / Lapsed

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