Semiconductor device with semi-metal

Claim 2

A semiconductor device comprising: a first semiconductor layer; a second semiconductor layer; a third semiconductor layer sandwiched between said first and second semiconductor layers; a first electrode ohmically contacting said first semiconductor layer; a second electrode ohmically contacting said second semiconductor layer; and a third electrode ohmically contacting at least said third semiconductor layer; said first and second semiconductor layers having substantially the same conduction bands and substantially the same valence bands when a bias voltage is not applied thereto; at the interface between said first and third semiconductor layers and between said second and third semiconductor layers, the energy level of the conduction band edge of said third semiconductor layer being lower than the energy level of the valence band edge of one of said first and second semiconductor layers, said third semiconductor layer having a thickness such that at least at the interface between said first and third semiconductor layers and between said second and third semiconductor layers, a semi-metal layer is formed.

Claim 3

A semiconductor device according to claim 1, wherein the interfaces between said first and third semiconductor layers and between said second and third semiconductor layers are heterojunctions.

Claim 4

A semiconductor device according to claim 1, wherein said first and second semiconductor layers comprise GaSb layers, and wherein said third semiconductor layer comprises an InAs layer, the thickness of said InAs layer being from 100 Å (1×10 -6 cm) to 200 Å (2×10 -6 cm).

Claim 5

A semiconductor device according to claim 1, wherein said third electrode ohmically contacting said first and second semiconductor layers with respect to carriers generated in said first and second semiconductor layers and at a portion in the vicinity of the interface between said first semiconductor layer and said third semiconductor layer and at a portion in the vicinity of the interface between said second semiconductor layer and said third semiconductor layer.

Claim 6

A semiconductor device comprising: a base layer having at least three layers including a GaSb/InAs/GaSb structure, outer layers in said GaSb/InAs/GaSb structure being GaSb layers, the InAs layer in said GaSb/InAs/GaSb structure having a thickness of between 100 Å (10 -6 cm) and 200 Å (2×10 -6 cm), whereby said GaSb/InAs/GaSb structure has a characteristic of a semi-metal; an emitter layer provided on a first side of said GaSb/InAs/GaSb structure; a collector layer provided on a second side of said GaSb/InAs/GaSb structure opposite the first side; a base electrode ohmically contacting at least the InAs layer in said GaSb/InAs/GaSb structure of said base layer; an emitter electrode provided on and ohmically contacting said emitter layer; and a collector electrode provided on and ohmically contacting said collector layer; whereby, by applying a voltage between said emitter electrode and said base electrode, carriers injected from said emitter later pass through said base layer as hot carriers to said collector layer.

Claim 7

A semiconductor device comprising: a base layer having at least three layers including a GaSb/InAs/GaSb structure, outer layers in said GaSb/InAs/GaSb structure being GaSb layers, the InAs layer in said GaSb/InAs/GaSb structure having a thickness of between 100 Å (10 -6 cm) and 200 Å (2×10 -6 cm), whereby said GaSb/InAs/GaSb structure has a characteristic of a semi-metal; an emitter layer provided on a first side of said GaSb/InAs/GaSb structure; a collector layer provided on a second side of said GaSb/InAs/GaSb structure opposite the first side; a base electrode ohmically contacting at least the InAs layer in said GaSb/InAs/GaSb structure of said base layer; an emitter electrode provided on and ohmically contacting said emitter layer; and a collector electrode provided on and ohmically contacting said collector layer; whereby, by applying a voltage between said emitter electrode and said base electrode, carriers injected from said emitter later pass through said base layer as hot carriers to said collector layer.

Claim 8

A semiconductor device according to claim 5, wherein said base electrode ohmically contacting all layers in said GaSb/InAs/GaSb structure.

Claim 9

A semiconductor device according to claim 5, wherein said emitter layer and said collector layer are GaSb layers.

Claim 10

A semiconductor device according to claim 5, wherein, at the interfaces between the GaSb layer and the InAs layer in said GaSb/InAs/GaSb structure, the conduction band edge of the InAs layer is lower than the valence band edge of the GaSb layer.

Claim 11

A semiconductor device according to claim 5, wherein the conductivity type of said GaSb/InAs/GaSb structure is n-n-n.

Claim 12

A semiconductor device according to claim 5, wherein the conductivity type of said GaSb/InAs/GaSb structure is p-p-p.

Claim 13

A semiconductor device according to claim 5, wherein said base layer comprises a plurality of periodic GaSb/InAs/GaSb structures forming a superlattice structure.

Claim 14

A semiconductor device comprising: a base layer having at least three layers including an InAs/GaSb/InAs structure, outer layers in said InAs/GaSb/InAs structure being InAs layers, each InAs layer in said InAs/GaSb/InAs structure having a thickness of between 100 Å (10 -6 cm) and 200 Å (2×10 -6 cm), whereby said InAs/GaSb/InAs structure has a characteristic of a semi-metal; an emitter layer provided on a first side of said InAs/GaSb/InAs structure; a collector layer provided on a second side of said InAs/GaSb/InAs structure the second side being opposite the first side; a first barrier layer provided between said base layer and said emitter layer, for preventing an injection of carriers from said emitter layer to said base layer when a bias voltage is not applied between said base layer and said emitter layer; a second barrier layer provided between said base layer and said collector layer, for preventing an injection of carriers from said collector layer to said base layer when a bias voltage is not applied between said base layer and said collector layer; a base electrode ohmically contacting at least the InAs layer in said InAs/GaSb/InAs structure of said base layer; an emitter electrode provided on ohmically contacting said emitter layer; and a collector electrode provided on and ohmically contacting said collector layer.

Claim 15

A semiconductor device comprising: a base layer having at least three layers including an InAs/GaSb/InAs structure, outer layers in said InAs/GaSb/InAs structure being InAs layers, each InAs layer in said InAs/GaSb/InAs structure having a thickness of between 100 Å (10 -6 cm) and 200 Å (2×10 -6 cm), whereby said InAs/GaSb/InAs structure has a characteristic of a semi-metal; an emitter layer provided on a first side of said InAs/GaSb/InAs structure; a collector layer provided on a second side of said InAs/GaSb/InAs structure the second side being opposite the first side; a first barrier layer provided between said base layer and said emitter layer, for preventing an injection of carriers from said emitter layer to said base layer when a bias voltage is not applied between said base layer and said emitter layer; a second barrier layer provided between said base layer and said collector layer, for preventing an injection of carriers from said collector layer to said base layer when a bias voltage is not applied between said base layer and said collector layer; a base electrode ohmically contacting at least the InAs layer in said InAs/GaSb/InAs structure of said base layer; an emitter electrode provided on ohmically contacting said emitter layer; and a collector electrode provided on and ohmically contacting said collector layer.

Claim 16

A semiconductor device according to claim 12, wherein said base electrode ohmically contacts all layers in said InAs/GaSb/InAs structure.

Claim 17

A semiconductor device according to claim 12, wherein said emitter layer and said collector layer are InAs layers.

Claim 18

A semiconductor device according to claim 12, wherein, at the interfaces between the GaSb layer and the InAs layer in said GaSb/InAs/GaSb structure, the conduction band edge of the InAs layer is lower than the valence band edge of the GaSb layer.

Claim 19

A semiconductor device according to claim 12, wherein the conductivity type of said InAs/GaSb/InAs structure is n-n-n.

Claim 20

A semiconductor device according to claim 12, wherein the conductivity type of said InAs/GaSb/InAs structure is p-p-p.

Claim 21

A semiconductor device according to claim 12, wherein said base layer has a plurality of periodic InAs/GaSb/InAs structures forming a superlattice structure.

Claim 22

A semiconductor device according to claim 12, wherein when a voltage is applied between said emitter electrode and said base electrode, carriers are injected from said emitter layer through said first barrier layer by tunneling to said base layer and are passed through minibands in said base layer.

Claim 23

A semiconductor device according to claim 12, wherein said first and second barrier layers are AlInAs layers.

Claim 24

A semiconductor device comprising: a base layer having at least three layers, each of said three layers including a first semiconductor material, a second semiconductor material, and said first semiconductor material structure, outer layers in said structure being said first semiconductor material layers, said second semiconductor material layer in said structure having a thickness such that at least at the interfaces between said first and second semiconductor material layers, a semi-metal is formed, and at the interfaces between said first and second semiconductor material layers, the energy level of the conduction band edge of each said second semiconductor material layer is lower than the energy level of the valence band edge of each said first semiconductor material layer; an emitter layer provided on a first side of said base layer structure; a collector layer provided on a second side of said base layer structure; a base electrode ohmically contacting at least said second semiconductor material layer in said base layer structure; an emitter electrode provided on and ohmically contacting said emitter layer; a collector electrode provided on and ohmically contacting said emitter layer; whereby, by applying a voltage between said emitter electrode and said base electrode, carriers injected from said emitter layer are passed through said base layer as hot carriers to said collector layer.

Claim 25

A semiconductor device comprising: a base layer having at least three layers, each of said three layers including a first semiconductor material, a second semiconductor material, and said first semiconductor material structure, outer layers in said structure being said first semiconductor material layers, said second semiconductor material layer in said structure having a thickness such that at least at the interfaces between said first and second semiconductor material layers, a semi-metal is formed, and at the interfaces between said first and second semiconductor material layers, the energy level of the conduction band edge of each said second semiconductor material layer is lower than the energy level of the valence band edge of each said first semiconductor material layer; an emitter layer provided on a first side of said base layer structure; a collector layer provided on a second side of said base layer structure; a base electrode ohmically contacting at least said second semiconductor material layer in said base layer structure; an emitter electrode provided on and ohmically contacting said emitter layer; a collector electrode provided on and ohmically contacting said emitter layer; whereby, by applying a voltage between said emitter electrode and said base electrode, carriers injected from said emitter layer are passed through said base layer as hot carriers to said collector layer.

Claim 26

A semiconductor device comprising: a base layer having at least three layers including; a first layer of a second semiconductor material; a second layer of a first semiconductor material formed on said first layer; and a third layer of a second semiconductor material formed on said second layer; outer layers in said structure being said second semiconductor material layers, said first semiconductor material layer in said structure having a thickness such that at least at the interfaces between said first and second semiconductor material layers, a semi-metal is formed, the energy level of the conduction band edge of each said first semiconductor material layer being lower than the energy level of the valence band edge of each said second semiconductor material layer; an emitter layer provided on a first side of said structure; a collector layer provided on a second side of said structure opposite the first side; a first barrier layer provided between said base layer and said emitter layer, for preventing an injection of carriers from said emitter layer to said base layer when a bias voltage is not applied between said base layer and said emitter layer; a second barrier layer provided between said base layer and said collector layer, for preventing an injection of carriers from said collector layer to said base layer when a bias voltage is not applied between said base layer and said collector layer; a base electrode ohmically contacting at least the second semiconductor material layer in said structure; an emitter electrode provided on and ohmically contacting said emitter layer; and a collector electrode provided on and ohmically contacting said collector layer.

Claim 27

A semiconductor device comprising: a base layer having at least three layers including; a first layer of a second semiconductor material; a second layer of a first semiconductor material formed on said first layer; and a third layer of a second semiconductor material formed on said second layer; outer layers in said structure being said second semiconductor material layers, said first semiconductor material layer in said structure having a thickness such that at least at the interfaces between said first and second semiconductor material layers, a semi-metal is formed, the energy level of the conduction band edge of each said first semiconductor material layer being lower than the energy level of the valence band edge of each said second semiconductor material layer; an emitter layer provided on a first side of said structure; a collector layer provided on a second side of said structure opposite the first side; a first barrier layer provided between said base layer and said emitter layer, for preventing an injection of carriers from said emitter layer to said base layer when a bias voltage is not applied between said base layer and said emitter layer; a second barrier layer provided between said base layer and said collector layer, for preventing an injection of carriers from said collector layer to said base layer when a bias voltage is not applied between said base layer and said collector layer; a base electrode ohmically contacting at least the second semiconductor material layer in said structure; an emitter electrode provided on and ohmically contacting said emitter layer; and a collector electrode provided on and ohmically contacting said collector layer.