US4914812A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of self-packaging an IC chip
Assignee: Intersil Corp
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Filing: 1989-02-17
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Granted: 1990-04-10
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Expires: 2009-02-17
Abstract
Abstract A method of self packaging an integrated circuit chip on a printed circuit board where conductive leads form an electrical connection with interconnect leads on the printed circuit board. A centering frame placed on the printed circuit board serves to align the leads. A cooling cap which dissipates heat from the integrated circuit chip is placed over the centering frame and integrated circuit chip. In one embodiment, the leads form a pressure fit and the cooling cap forces the pressure-fit electrical connections. In another embodiment, the leads make rubbing contact with each other.
Inventors
- 👤 Harold F. Webster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:42
CPC Classifications
H; H10; H10W; H10W40/00; H10W40/20; H10W40/22; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/325; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49128; Y10T29/4913; Y10T29/49146
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
109 words
A method of self packaging an integrated circuit chip on a printed circuit board wherein conductive leads extending from terminals on said chip form a pressure-fit electrical connection with interconnect leads positioned on said printed circuit board, comprising the steps of: securing conductive leads to an integrated circuit chip; cementing said conductive leads to a compliant backing member disposed about a periphery of said integrated circuit chip; aligning said conductive leads with corresponding interconnect leads on a printed circuit board; and applying a cap over said integrated circuit chip onto said printed circuit board, said cap forcing said conductive leads and said interconnect leads to form pressure-fit electrical connections.
Claim 2
Independent Claim
109 words
A method of self packaging an integrated circuit chip on a printed circuit board wherein conductive leads extending from terminals on said chip form a pressure-fit electrical connection with interconnect leads positioned on said printed circuit board, comprising the steps of: securing conductive leads to an integrated circuit chip; cementing said conductive leads to a compliant backing member disposed about a periphery of said integrated circuit chip; aligning said conductive leads with corresponding interconnect leads on a printed circuit board; and applying a cap over said integrated circuit chip onto said printed circuit board, said cap forcing said conductive leads and said interconnect leads to form pressure-fit electrical connections.
Claim 3
Dependent Claim
83 words
A method of self packaging an integrated circuit chip as recited in claim 15 wherein said step of aligning comprises the steps of: providing a centering frame positioned on said printed circuit board, said centering frame having an aperture partially exposing said interconnect leads on said printed circuit board, said aperture having side walls; and placing said integrated circuit chip in said aperture, said side walls of said aperture in said centering frame serving to align said conductive leads with said interconnect leads.
Claim 4
Independent Claim
106 words
A method of self packaging an integrated circuit chip on a printed circuit board wherein conductive leads extending from terminals on said chip make rubbing contact with interconnect leads extending from said printed circuit board, comprising the steps of: securing conductive leads to an integrated circuit chip; cementing said conductive leads to a compliant backing member disposed about a periphery of said integrated circuit chip; aligning said conductive leads with corresponding interconnect leads extending from a printed circuit board; and applying a cap over said integrated circuit chip onto said printed circuit board, said cap retaining said integrated circuit in position atop said printed circuit board.
Claim 5
Independent Claim
106 words
A method of self packaging an integrated circuit chip on a printed circuit board wherein conductive leads extending from terminals on said chip make rubbing contact with interconnect leads extending from said printed circuit board, comprising the steps of: securing conductive leads to an integrated circuit chip; cementing said conductive leads to a compliant backing member disposed about a periphery of said integrated circuit chip; aligning said conductive leads with corresponding interconnect leads extending from a printed circuit board; and applying a cap over said integrated circuit chip onto said printed circuit board, said cap retaining said integrated circuit in position atop said printed circuit board.
Claim 6
Dependent Claim
87 words
A method of self packaging an integrated circuit chip as recited in claim 3 wherein said step of aligning comprises the steps of: providing a centering frame positioned on said printed circuit board, said centering frame having an aperture exposing said interconnect leads extending from said printed circuit board, said aperture having side walls supporting said interconnect leads; and placing said integrated circuit chip in said aperture, said side walls of said aperture in said centering frame serving to align said conductive leads with said interconnect leads.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-09 | 1993-10-09 | 1994-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-09 | 1997-10-09 | 1998-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-09 | 2001-10-09 | 2002-04-10 | $7700.00 | Window Closed / Lapsed |