Intergrated logic circuit having testing function circuit formed integrally therewith

Claim 2

A circuit having a testing function, comprising: a plurality of circuit portions constituting a data processing circuit having an operation mode and a test mode, each having different number of bits to be processed therein: a plurality of testing circuits, each having an independent input, provided corresponding to said plurality of circuit portions, each of said plurality of testing circuits being interposed between an output of one of said circuit portions corresponding to said testing circuit and an input of another of said circuit portions each of said plurality of testing circuits having an additional input connected to a respective input of said circuit portion corresponding to said testing circuit, whereby, responsive to signals on said independent inputs of said testing circuits, said plurality of circuit portions are made to function as said data processing circuit in said operation mode, and are selectively isolated or bypassed for testing the corresponding circuit portion to output test data obtained from each processed bit in synchronization in said test mode.

Claim 3

A circuit having testing function according to claim 1, wherein each of said plurality of circuit portions comprises one or more input terminals (11˜31) and one or more output terminals (12˜32); each of said plurality of testing circuits comprises one or more scan latch circuits, the number of which is equal to the number of the output terminals of the corresponding circuit portion, and, additionally, when the number of the output terminals of the corresponding circuit portion is not equal to the number of the output terminals of the circuit portion having maximum number of bits to be processed, one or more latch circuits, the number of which is equal to the difference between the number of output terminals and the maximum number of bit to be processed.

Claim 4

A circuit having testing function according to claim 2, wherein a plurality of sets of circuit elements are constituted by said plurality of circuit portions and the corresponding testing circuits, said circuit elements being connected in series with each other.

Claim 5

A circuit having testing function according to claim 3, wherein said scan latch circuits and said latch circuits correspond to respective bits to be processed in said plurality of circuit portions, the scan latch circuit of one circuit element comprising a first input terminal, a second input terminal, a control terminal and a scan output terminal, and the latch circuit of said one circuit element comprising a latch input terminal and a latch output terminal; said first input terminal connected to the output terminal of the corresponding circuit portion, said second input terminal connected to the input terminal of the corresponding circuit portion or to the scan output terminal of the scan latch circuit and the latch output terminal of the latch circuit in a testing circuit corresponding to the circuit element preceding said one circuit being inputted to said control signal being inputted to said control terminal, and said scan output terminal connected to the input terminal of the circuit portion of a succeeding circuit element to which said one circuit element is connected, to the second input terminal of the scan latch circuit or to the input terminal of the latch circuit in the circuit element of said succeeding circuit element; and said latch input terminal connected to the scan output terminal of the scan latch circuit or the latch output terminal of the latch circuit in the circuit element of said preceding stage, and said latch output terminal connected to the input terminal of the circuit portion of the circuit element of said succeeding stage, to the second input terminal of the scan latch circuit or to the latch input terminal of the latch circuit in the testing circuit.

Claim 6

A circuit having testing function according to claim 4, wherein said control signal comprises a first signal state defining the operation mode and a second signal state defining the test mode, said first input terminal and said scan output terminal are electrically conducted by the application of said control signal of said first state to said control terminal, and said second input terminal and scan output terminal are electrically conducted by the application of said control signal of said second signal state to said control terminal.

Claim 7

A circuit having testing function according to claim 4, comprising data input terminals whose number being equal to said maximum number of bits to be processed, to which data to be processed or data for testing are inputted; and data output terminals whose number being equal to that of said data input terminals from which processed data or tested data are outputted; each of said data input terminals connected to each of the input terminals of the circuit portion and to each of the second input terminals or each of the scan input terminals of the testing circuit of one circuit element, each of said data output terminals connected to each of the scan output terminals of the scan latch circuit and each of the latch output terminal of the latch circuit of the test circuit in another circuit element.

Claim 8

A circuit having testing function according to claim 2, wherein scan circuits and the latch circuits included in each of said plurality of testing circuits synchronously output data.

Claim 9

A circuit having testing function according to claim 7, wherein synchronized clock signals are applied to the scan latch circuit and the latch circuit included in each of said plurality of testing circuits.

Claim 10

A circuit having testing function, comprising: a plurality of circuit portions constituting a data processing circuit having an operation mode and a test mode; a plurality of testing means each having independent inputs provided corresponding to said plurality of circuit portions, for making said plurality of circuit portions function as said data processing circuit in said operation mode and testing corresponding circuit portions independently in said test mode by concurrently bypassing at least another said circuit portion in said test mode, whereby, responsive to signals on said independent inputs of said testing circuits, said plurality of circuit portions are made to function as said data processing circuit in said operation mode, and are selectively isolated or bypassed for testing the corresponding circuit portion to output test data obtained from each processed bit in synchronization in said test mode.

Claim 11

A circuit having testing function, comprising: a plurality of circuit portions constituting a data processing circuit having an operation mode and a test mode; a plurality of testing means each having independent inputs provided corresponding to said plurality of circuit portions, for making said plurality of circuit portions function as said data processing circuit in said operation mode and testing corresponding circuit portions independently in said test mode by concurrently bypassing at least another said circuit portion in said test mode, whereby, responsive to signals on said independent inputs of said testing circuits, said plurality of circuit portions are made to function as said data processing circuit in said operation mode, and are selectively isolated or bypassed for testing the corresponding circuit portion to output test data obtained from each processed bit in synchronization in said test mode.