Comparator circuits

Claim 2

Comparator means comprising: at least two comparators, having a common input and separate outputs, constructed so that an input signal causes an output signal from each output, said output signals being of the opposite sense; a bistable circuit connected to the outputs of the comparators, said comparators being connected in anti-phase, with the separate comparator outputs being combined by said bistable circuit to produce a single switching signal, and wherein the comparators are connected to the bistable circuit via logical gating operable to combine the comparator outputs to a single signal to be supplied to the toggle input of the bistable circuit.

Claim 3

Comparator means according to claim 1 wherein the logical gating comprises a NOR gate.

Claim 4

A comparator circuit for supplying a binary signal indicative of whether the level of a received analog input signal is greater or less than a predetermined reference level, the comparator circuit comprising: input means for receiving said analog input signal; reference level defining means for making available said predetermined reference level; first and second comparator amplifiers each having an inverting input and a non-inverting input, the inverting input of the first comparator amplifier and the non-inverting of the second being connected to said input means and the non-inverting input of the first comparator amplifier and the inverting input of the second being connected to said reference level defining means for the two comparator amplifiers to produce conjugate binary output signals which undergo transitions between a high and a low level in respective opposite directions in response to each of any crossings of the reference level by the input signal level; and logic circuit means including a bistable device coupled to the comparator amplifiers for switching between the two output states of the bistable device to be initiated, following any one of said reference level crossings, by that one of the resultant comparator amplifier output signal transitions which is in a predetermined one of said directions.

Claim 5

A comparator circuit for supplying a binary signal indicative of whether the level of a received analog input signal is greater or less than a predetermined reference level, the comparator circuit comprising: input means for receiving said analog input signal; reference level defining means for making available said predetermined reference level; first and second comparator amplifiers each having an inverting input and a non-inverting input, the inverting input of the first comparator amplifier and the non-inverting of the second being connected to said input means and the non-inverting input of the first comparator amplifier and the inverting input of the second being connected to said reference level defining means for the two comparator amplifiers to produce conjugate binary output signals which undergo transitions between a high and a low level in respective opposite directions in response to each of any crossings of the reference level by the input signal level; and logic circuit means including a bistable device coupled to the comparator amplifiers for switching between the two output states of the bistable device to be initiated, following any one of said reference level crossings, by that one of the resultant comparator amplifier output signal transitions which is in a predetermined one of said directions.

Claim 6

A comparator circuit according to claim 3, wherein, for each comparator amplifier, output level transitions in said opposite directions become fully executed after respective different response times following each reference level crossing and wherein said predetermined one of said directions is the one for which the response time is least.

Claim 7

A comparator circuit according to claim 3, wherein said bistable device has a clock input and the bistable device is operable for being toggled between its two output states by pulse signals received at its clock input, said logic circuit means further including a NOR gate having inputs connected to outputs of respective ones of the comparator amplifiers and an output connected to the clock input of the bistable device.

Claim 8

A comparator circuit according to claim 5, wherein said bistable device further comprises a set input and a reset input and the device is operable for being set into one of its output states by a set signal received at its set input and for being reset to its other output state by a reset signal received at its reset input, said set and reset inputs being connected to the outputs of respective ones of the comparator amplifiers.

Claim 9

A comparator circuit according to claim 3, wherein said bistable device comprises a set input and a reset input and the device is operable for being set into one of its output states by a set signal received at its set input and for being reset to its other output state by a reset signal received at its reset input, said set and reset input being connected to the outputs of the comparator amplifiers via ac coupling components, with the logic circuit means further including rectifier diodes connected to said set and reset inputs of the bistable device for limiting a magnitude of any pulses having one polarity received from the ac coupling components while not limiting pulses having an opposite polarity.

Claim 10

A comparator according to claim 7, wherein said ac coupling components comprise respective capacitors connected in series between the outputs of the comparator amplifiers and the associated inputs of the bistable device, and respective resistors connected between the inputs of the bistable device and a common zero potential conductor of the circuit, said rectifier diodes being connected in parallel with respective ones of said resistors.