US4910416A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power switch monitor to improve switching time
Assignee: Schneider Electric USA Inc
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Filing: 1988-03-04
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Granted: 1990-03-20
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Expires: 2008-03-04
Abstract
Abstract The present invention provides an improved device for minimizing the time delays associated with turning on and off the power switches or power transistors in a standard totem pole configuration. An improved saturation detector monitors each transistor to determine when it is in saturation and generates a feedback signal which is combined with the input signal to generate the appropriate time delay needed to improve the switching time of the transistor.
Inventors
- 👤 Michael D. Salcone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:31
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K17/042; H03K17/04213; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/665; H03K17/666
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
103 words
In a switching circuit comprising first and second transistors electrically connected to an input signal in a totem pole configuration, first and second drivers electrically connected to said first and second transistors, respectively, for driving same, first and second shunt diodes electrically connected across said first and second transistors, respectively, a power supply and a load, the improvement in combination therewith comprising a saturation detector connected to each of said first and second transistors for monitoring the saturation state of the respective transistor and generating a feedback signal which is combined with said input signal to improve the switching time of the transistors.
Claim 2
Dependent Claim
103 words
In a switching circuit comprising first and second transistors electrically connected to an input signal in a totem pole configuration, first and second drivers electrically connected to said first and second transistors, respectively, for driving same, first and second shunt diodes electrically connected across said first and second transistors, respectively, a power supply and a load, the improvement in combination therewith comprising a saturation detector connected to each of said first and second transistors for monitoring the saturation state of the respective transistor and generating a feedback signal which is combined with said input signal to improve the switching time of the transistors.
Claim 3
Dependent Claim
21 words
The improvement described in claim 1 wherein the feedback signal is combined with the input signal in a time delay means.
Claim 4
Dependent Claim
105 words
The improvement described in claim 2 wherein the time delay means comprises: (a) an inverter means connected to said input signal for generating an inverted input signal; (b) a first time delay means connected to said input signal and second saturation means for combining the input signal with the saturation signal from the second transistor and sending an activation signal to the first transistor; and (c) a second time delay means connected to said inverted input means and said first saturation means for combining the inverted input signal with the saturation signal from the first transistor and sending an activation signal to the second transistor.
Claim 5
Dependent Claim
32 words
The improvement described in claim 3 wherein the first time delay means comprises an AND gate and a driver and the second time delay means comprises an AND gate and a driver.
Claim 6
Dependent Claim
71 words
The improvement described in claim 4 wherein the saturation detector for one transistor comprises: (a) a test current generator connected between the transistor collector and emitter for generating a test current; (b) a comparator connected to the transistor collector and emitter for comparing the voltages thereof such that when the voltages are unequal, the test current is diverted to the comparator rather than being allowed to flow to the transistor; and
Claim 7
Dependent Claim
109 words
The improvement described in claim 3 wherein the saturation detector for one transistor comprises: (a) a test current generator connected between the transistor collector and emitter for generating a test current; (b) a comparator connected to the transistor collector and emitter for comparing the voltages thereof such that when the voltages are unequal, the test current is diverted to the comparator rather than being allowed to flow to the transistor; and (c) a sensor which detects when the test current is flowing to the transistor and generates a feedback signal. (c) a sensor which detects when the test current is flowing to the transistor and generates a feedback signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-19 | 1993-09-18 | 1994-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-19 | 1997-09-18 | 1998-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-19 | 2001-09-18 | 2002-03-20 | $7700.00 | Window Closed / Lapsed |