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US4908818A Expired / Lapsed US ⏱️ 0.0 years remaining

Multiplex communication arrangement capable of selectively monitoring active multiplexers and of simultaneously checking an input to a stand-by demultiplexer

Assignee: NEC Corp
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Filing: 1987-06-25
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Granted: 1990-03-13
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Expires: 2007-06-25
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Abstract

Abstract In a multiplex communication arrangement of an N:1 redundancy configuration, each multiplexer comprises a multiplexing circuit for multiplexing a plurality of multiplexer input signals into a multiplexed signal and an encoder for encoding the multiplexed signal into an encoded signal of self-checking codes, such as the known CRC codes. Into a decoder output signal, a decoder of each demultiplexer decodes a demultiplexer input signal which is in a form of the self-checking codes. As a selected signal, a selector selects one of the decoder output signal and the multiplexed signal produced in one of the multiplexers, (N+1) in number, that the selector selects as a selected multiplexer. A demultiplexing circuit demultiplexes the selected signal into a plurality of demultiplexer output signals. A bit-by-bit comparator compares the multiplexer input signal of the selected multiplexer with the demultiplexer output signals which are produced in one of the demultiplexers, (N+1) in number, for the multiplexed signal produced in the selected multiplexer. Inasmuch as such demultiplexer produces the demultiplexer output signals for a utilization device when the demultiplexer in question is an active one, it follows that the above-mentioned one of the demultiplexers is a stand-by one.

Inventors

  • 👤 Osamu Kawano

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 10:48
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/14

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 223 words
A multiplex communication arrangement which comprises: (A) N+1 multiplexers, N being a positive integer greater than 1, each multiplexer being for connection to a respective transmission channel and comprising a multiplexing circuit for multiplexing a plurality of multiplexer input signals applied thereto into a multiplexed signal and an encoder for encoding said multiplexed signal into an encoded signal of self-checking codes for transmission to its respective said transmission channel; (B) N+1 demultiplexers each for connection to a respective reception channel, each demultiplexer comprising: (1) a decoder for decoding a demultiplexer input signal applied thereto into a decoder output signal, said demultiplexer input signal being in a form of said self-checking codes and being received through its respective reception channel, said decoder checking for errors in said demultiplexer input signal applied thereto; (2) a selector for selecting, as a selected signal, one of said decoder output signal and the multiplexed signal produced by one of said multiplexers that said selector selects as a selected multiplexer; and (3) a demultiplexing circuit for demultiplexing said selected signal into a plurality of demultiplexer output signals; and (C) a comparator for carrying out bit by bit comparison of the multiplexer input signals of said selected multiplexer with the demultiplexer output signals which are produced from one of said demultiplexers for the multiplexed signal produced in said selected multiplexer.
Claim 2
Dependent Claim 223 words
A multiplex communication arrangement which comprises: (A) N+1 multiplexers, N being a positive integer greater than 1, each multiplexer being for connection to a respective transmission channel and comprising a multiplexing circuit for multiplexing a plurality of multiplexer input signals applied thereto into a multiplexed signal and an encoder for encoding said multiplexed signal into an encoded signal of self-checking codes for transmission to its respective said transmission channel; (B) N+1 demultiplexers each for connection to a respective reception channel, each demultiplexer comprising: (1) a decoder for decoding a demultiplexer input signal applied thereto into a decoder output signal, said demultiplexer input signal being in a form of said self-checking codes and being received through its respective reception channel, said decoder checking for errors in said demultiplexer input signal applied thereto; (2) a selector for selecting, as a selected signal, one of said decoder output signal and the multiplexed signal produced by one of said multiplexers that said selector selects as a selected multiplexer; and (3) a demultiplexing circuit for demultiplexing said selected signal into a plurality of demultiplexer output signals; and (C) a comparator for carrying out bit by bit comparison of the multiplexer input signals of said selected multiplexer with the demultiplexer output signals which are produced from one of said demultiplexers for the multiplexed signal produced in said selected multiplexer.
Claim 3
Dependent Claim 79 words
A multiplex communication arrangement as claimed in claim 1, the multiplexed signal being produced in each multiplexer together with a first synchronizing signal, the decoder output signal being produced in each demultiplexer together with a second synchronizing signal, wherein the demultiplexing circuit of each demultiplexer is for demultiplexing the selected signal into the demultiplexer output signals with reference to said first and said second synchronizing signals when the selected signal is the multiplexed and the decoder output signals, respectively.
Claim 4
Dependent Claim 42 words
A multiplex communication arrangement as claimed in claim 2, wherein the decoder of each demultiplexer is furthermore for establishing synchronism of the demultiplexer input signal and for carrying out error detection on the demultiplexer input signal with reference to said self-checking codes.
Claim 5
Dependent Claim 27 words
A multiplex communication arrangement as claimed in claim 3, wherein said one of the demultiplexers is a stand-by demultiplexer when the selector thereof selects said selected multiplexer.

References Cited (Backward Citations)

US4160877A Cited
US4631719A Cited
US4601028A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-03-12 1993-09-11 1994-03-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-03-12 1997-09-11 1998-03-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-03-12 2001-09-11 2002-03-13 $7700.00 Window Closed / Lapsed

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