US4908566A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage regulator having staggered pole-zero compensation network
Assignee: Intersil Corp
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Filing: 1989-02-22
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Granted: 1990-03-13
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Expires: 2009-02-22
Abstract
Abstract The feedback control loop of the common-emitter output transistor stage of a low dropout voltage regulator imcorporates a staggered pole-zero network, which effectively introduces an incremental reduction, or rolloff, in gain, and an accompanying reduction in phase shift with increase in frequency, so that, at the unity gain point of the transfer characteristic, there is still substantial phase margin, thus preventing the circuit from being driven into oscillation. The RC load pole location can vary widely and stability is maintained. The network is configured as a staggered resistor-capacitor network comprised of plural resistor-capacitor circuits coupled in cascade between the output of the feedback error amplifier and the input of a buffer amplifier the output of which drives the base of the output stage transistor in order to offset loading effects of the transistor base on the staggered pole-zero network.
Inventors
- 👤 Bruce J. Tesch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:46
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
162 words
A voltage regulator circuit comprising: an output amplifier stage having an input terminal to which an unregulated input voltage is coupled, an output terminal from which a regulated output voltage is derived, and a control terminal to which a control voltage is applied; an error amplifier stage having a first input coupled to said output terminal, a second input coupled to receive a reference voltage, and an output from which an error voltage representative of the difference between said regulated output voltage and said voltage is coupled as said control voltage for said output amplifier stage; and means, coupled in a feedback path from said output terminal through said error amplifier stage to said control terminal, for maintaining the open loop phase differential between the first input of said error amplifier stage and the output terminal of said output amplifier stage less than 360° for the entirety of the frequency range over which the gain is equal to or greater than unity.
Claim 2
Dependent Claim
162 words
A voltage regulator circuit comprising: an output amplifier stage having an input terminal to which an unregulated input voltage is coupled, an output terminal from which a regulated output voltage is derived, and a control terminal to which a control voltage is applied; an error amplifier stage having a first input coupled to said output terminal, a second input coupled to receive a reference voltage, and an output from which an error voltage representative of the difference between said regulated output voltage and said voltage is coupled as said control voltage for said output amplifier stage; and means, coupled in a feedback path from said output terminal through said error amplifier stage to said control terminal, for maintaining the open loop phase differential between the first input of said error amplifier stage and the output terminal of said output amplifier stage less than 360° for the entirety of the frequency range over which the gain is equal to or greater than unity.
Claim 3
Dependent Claim
15 words
A voltage regulator circuit according to claim 1, wherein said means comprises a resistor-capacitor network.
Claim 4
Dependent Claim
36 words
A voltage regulator circuit according to claim 1, wherein said means comprises a plurality of resistor-capacitor stages coupled in cascade between the output of said error amplifier and the control terminal of said output amplifier stage.
Claim 5
Dependent Claim
90 words
A voltage regulator circuit according to claim 3, wherein each resistor-capacitor stage comprises an input node, an output node and a reference voltage node, and includes a first resistor coupled between said input and output nodes and a series connection of a second resistor and a capacitor coupled between said output node and said reference voltage node, and wherein said resistor-capacitor stages are cascaded such that the first resistors thereof are coupled in series between the output of said error amplifier and the control terminal of said output amplifier stage.
Claim 6
Dependent Claim
55 words
A voltage regulator circuit according to claim 4, wherein said output amplifier stage comprises a common-emitter configured bipolar transistor, the emitter of which is coupled to said unregulated input terminal, the base of which is coupled to said control terminal through a buffer stage and the collector of which is coupled to said output terminal.
Claim 7
Dependent Claim
26 words
A voltage regulator circuit according to claim 4, wherein the values of the capacitors of respective ones of said resistor-capacitor stages are different from one another.
Claim 8
Independent Claim
174 words
A method of maintaining stable operation of a voltage regulator circuit which comprises an output amplifier stage having an input terminal to which an unregulated input voltage is coupled, an output terminal from which a regulated output voltage is derived for application to an output load, and a control terminal to which a control voltage is applied; and an error amplifier stage having a first input coupled to said output terminal, a second input coupled to receive a reference voltage, and an output from which an error voltage representative of the difference between said regulated output voltage and said reference voltage is coupled as said control voltage for said output amplifier stage; said method maintaining stable operation of said regulator circuit over the entirety of the frequency range over which gain is equal to or greater than unity, irrespective of the pole-zero characteristics of the output load, comprising the steps of: providing a staggered hole-zero compensation network in a feedback path from said output terminal through said error amplifier stage to said control terminal.
Claim 9
Independent Claim
174 words
A method of maintaining stable operation of a voltage regulator circuit which comprises an output amplifier stage having an input terminal to which an unregulated input voltage is coupled, an output terminal from which a regulated output voltage is derived for application to an output load, and a control terminal to which a control voltage is applied; and an error amplifier stage having a first input coupled to said output terminal, a second input coupled to receive a reference voltage, and an output from which an error voltage representative of the difference between said regulated output voltage and said reference voltage is coupled as said control voltage for said output amplifier stage; said method maintaining stable operation of said regulator circuit over the entirety of the frequency range over which gain is equal to or greater than unity, irrespective of the pole-zero characteristics of the output load, comprising the steps of: providing a staggered hole-zero compensation network in a feedback path from said output terminal through said error amplifier stage to said control terminal.
Claim 10
Dependent Claim
34 words
A method according to claim 7, wherein said step comprises coupling a plurality of resistor-capacitor stages in cascade between the output of said error amplifier and the control terminal of said output amplifier stage.
Claim 11
Dependent Claim
89 words
A method according to claim 8, wherein each resistor-capacitor stage comprises an input node, an output node and a reference voltage node, and includes a first resistor coupled between said input and output nodes and a series connection of a second resistor and a capacitor coupled between said output node and said reference voltage node, and wherein said resistor capacitor stages are cascaded such that the first resistors thereof are coupled in series between the output of said error amplifier and the control terminal of said output amplifier stage.
Claim 12
Dependent Claim
53 words
A method according to claim 9, wherein said output amplifier stage comprises a common-emitter configured bipolar transistor, the emitter of which is coupled to said unregulated input terminal, the base of which is coupled to said control terminal through a buffer stage and the collector of which is coupled to said output terminal.
Claim 13
Dependent Claim
24 words
A method according to claim 8, wherein the values of the capacitors of respective ones of said resistor-capacitor stages are different from one another.
Claim 14
Dependent Claim
164 words
A voltage regulator circuit comprising: an output amplifier stage having an input terminal to which an unregulated input voltage is coupled, an output terminal from which a regulated output voltage is derived for application to an output load, and a control terminal to which a control voltage is applied; an error amplifier stage having a first input coupled to said output terminal, a second input coupled to receive a reference voltage, and an output from which an error voltage representative of the difference between said regulated output voltage and said reference voltage is coupled as said control voltage for said output amplifier stage; and means for maintaining stable operation of said regulator circuit over the entirety of the frequency range over which gain is equal to or greater than unity irrespective of the pole-zero characteristics of the output load, said means comprising a staggered pole-zero compensation network in a feedback path from said output terminal through said error amplifier stage to said control terminal.
Claim 15
Dependent Claim
164 words
A voltage regulator circuit comprising: an output amplifier stage having an input terminal to which an unregulated input voltage is coupled, an output terminal from which a regulated output voltage is derived for application to an output load, and a control terminal to which a control voltage is applied; an error amplifier stage having a first input coupled to said output terminal, a second input coupled to receive a reference voltage, and an output from which an error voltage representative of the difference between said regulated output voltage and said reference voltage is coupled as said control voltage for said output amplifier stage; and means for maintaining stable operation of said regulator circuit over the entirety of the frequency range over which gain is equal to or greater than unity irrespective of the pole-zero characteristics of the output load, said means comprising a staggered pole-zero compensation network in a feedback path from said output terminal through said error amplifier stage to said control terminal.
Claim 16
Dependent Claim
38 words
A voltage regulator circuit according to claim 12, wherein said pole-zero compensation network comprises a plurality of resistor-capacitor stages coupled in cascade between the output of said error amplifier and the control terminal of said output amplifier stage.
Claim 17
Dependent Claim
91 words
A voltage regulator circuit according to claim 13, wherein each resistor-capacitor stage comprises an input node, an output node and a reference voltage node, and includes a first resistor coupled between said input and output nodes and a series connection of a second resistor and a capacitor coupled between said output node and said reference voltage node, and wherein said resistor capacitor stages are cascaded such that the first resistors thereof are coupled in series between the output of said error amplifier and the control terminal of said output amplifier stage.
Claim 18
Dependent Claim
55 words
A voltage regulator circuit according to claim 14, wherein said output amplifier stage comprises a common-emitter configured bipolar transistor, the emitter of which is coupled to said unregulated input terminal, the base of which is coupled to said control terminal through a buffer stage and the collector of which is coupled to said output terminal.
Claim 19
Dependent Claim
26 words
A voltage regulator circuit according to claim 13, wherein the values of the capacitors of respective ones of said resistor-capacitor stages are different from one another.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-12 | 1993-09-11 | 1994-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-12 | 1997-09-11 | 1998-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-12 | 2001-09-11 | 2002-03-13 | $7700.00 | Window Closed / Lapsed |