Successive approximation analog to digital converter

Claim 1

A successive approximation analog to digital converter, comprising: a local digital to analog converter for sampling an input analog signal to be held therein prior to a successive bit comparison from a most significant bit to a least significant bit of a digital signal to be obtained, and including a capacitor array composed of plural capacitors, a number of said plural capacitors being dependent on a number of bits of said digital signal, and each of said plural capacitors being connected to a common connecting point and to a switch connected to lines for said input analog signal, and first and second predetermined reference voltages, respectively; a first comparator for comparing a voltage of said common connecting point of said capacitor array and a middle point voltage between said first and second predetermined voltages to produce content signals of said bits for said digital signal; a successive approximation register for supplying a control digital signal dependent on said bit order to said local digital to analog converter to turn said switch on a terminal of one line selected from said lines dependent on said bit order, said control digital signal controlling said common connecting point voltage to be changed dependent on said bit order, and for receiving and storing said content signals to provide said digital signal; second and third comparators for comparing a voltage of said input analog signal and a third predetermined reference voltage and for comparing said voltage of said input analog signal and a fourth predetermined reference voltage, respectively, said third predetermined reference voltage being greater than said fourth predetermined reference voltage, thereby producing a first control signal where said voltage of said input analog signal is between said third and fourth predetermined reference voltages and a second control signal where said input analog signal is outside a voltage range between said third and fourth predetermined reference voltages; and a control means for controlling said local digital to analog converter and said successive approximation register to conduct said successive bit comparison from said most significant bit to said least significant bit when said first control signal is produced, and to conduct said successive bit comparison from a second significant bit to said least significant bit without a bit comparison of said most significant bit, a content of said most significant bit being determined by a comparison of said voltage of said input analog signal with said third and fourth predetermined reference voltages, when said second control signal is produced.