Synchronous receiver with direct mixing

Claim 2

A direct conversion synchronous receiver which tunes the frequency of an oscillator signal to an input signal, comprising: a phase-lock loop including a regulating filter, a voltage controlled oscillator controlled by an output of said regulating filter to generate first and second oscillator signals which are respectively 90 degrees out of phase with one another, and a first phase detector in the form of an amplitude demodulator which synchronously demodulates an input signal by mixing the input signal with the second oscillator signal to produce a first mixed signal, said regulating filter filtering the first mixed signal, such that the first oscillator signal is tuned in frequency and phase to that of the input signal; a second phase detector which demodulates the input signal by mixing the input signal with the first oscillator signal to produce a second mixed signal; first and second low-pass filter means respectively coupled to said first and second phase detectors, for respectively low-pass filtering the first and second mixed signals, means, coupled to said first and second filter means for quadrating the respective low-pass filtered outputs of said first and second filter means; means for summing together the quadrated outputs of said quadrating means to obtain a square law envelope signal; and means for making the envelope signal audible or visible during tuning.

Claim 3

A synchronous receiver as in claim 1, wherein said means for making the envelope signal audible or visible during tuning comprises means for making the low-pass filtered output of said first filter means audible or visible, including means, responsive to at least one of the low-pass filter outputs, for preventing at least in part, the low-pass filtered output of said second filter means from reaching said means for making the envelope signal audible or visible during the tuning.

Claim 4

A synchronous receiver as in claim 1, further comprising one of a switch, a potentiometer and a fade-over device coupling an output of said summing means to said means for making the envelope signal audible or visible during tuning.

Claim 5

A synchronous receiver as in claim 3, wherein said one of a switch, a potentiometer and a fade-over device couples the output of said second filter means to said means for making the envelope signal audible or visible during tuning, said receiver further comprising means for controlling said one of a switch, a potentiometer and a fade-over device to adjust relative amounts of the envelope signal and the second mixed signal passed through said one of a switch, a potentiometer and a fade-over device to said means for making the envelope signal audible or visible during the tuning.

Claim 6

A synchronous receiver as in claim 3, wherein said one of a switch, a potentiometer and a fade-over device is a switch which alternatively couples the output of said second filter means and the output of the summing means to said means for making the envelope signal audible or visible during tuning.

Claim 7

A synchronous receiver as in claim 5, wherein said receiver further comprising means, responsive to at least one of said first and second mixed signals for controlling said switch as a function of the coincidence of the frequency of the input signal and second mixed signal.

Claim 8

A direct conversion synchronous receiver having an input port and an output port, which fine tunes the frequency of an oscillator signal to a modulated audio or video input signal received at the input port and provides at the output port a demodulated signal for driving an audio or video transceiver, comprising: a phase-lock loop including a regulating filter, a voltage controlled oscillator means, controlled by an output of said regulating filter to generate first and second oscillator signals which are respectively 90 degrees out of phase with one another, and a first phase detector in the form of an amplitude demodulator which synchronously demodulates an input signal by mixing the input signal with the second oscillator signal to produce a first mixed signal, said regulating filter filtering the first mixed signal, such that the first oscillator signal is tuned in frequency and phase to that of the input signal; a second phase detector which demodulates the input signal by mixing the input signal with the first oscillator signal to produce a second mixed signal; first and second low-pass filter means respectively coupled to said first and second phase detectors, for respectively low-pass filtering the first and second mixed signals, means, coupled to said first and second filter means for quadrating the respective low-pass filtered outputs of said first and second filter means; means for summing together the quadrated outputs of said quadrating means to obtain a square law envelope signal; and an output port; and means for selectively applying at least a portion of the square law envelope signal to said output port during tuning.

Claim 9

A direct conversion synchronous receiver having an input port and an output port, which fine tunes the frequency of an oscillator signal to a modulated audio or video input signal received at the input port and provides at the output port a demodulated signal for driving an audio or video transceiver, comprising: a phase-lock loop including a regulating filter, a voltage controlled oscillator means, controlled by an output of said regulating filter to generate first and second oscillator signals which are respectively 90 degrees out of phase with one another, and a first phase detector in the form of an amplitude demodulator which synchronously demodulates an input signal by mixing the input signal with the second oscillator signal to produce a first mixed signal, said regulating filter filtering the first mixed signal, such that the first oscillator signal is tuned in frequency and phase to that of the input signal; a second phase detector which demodulates the input signal by mixing the input signal with the first oscillator signal to produce a second mixed signal; first and second low-pass filter means respectively coupled to said first and second phase detectors, for respectively low-pass filtering the first and second mixed signals, means, coupled to said first and second filter means for quadrating the respective low-pass filtered outputs of said first and second filter means; means for summing together the quadrated outputs of said quadrating means to obtain a square law envelope signal; and an output port; and means for selectively applying at least a portion of the square law envelope signal to said output port during tuning.

Claim 10

A synchronous receiver as in claim 7, wherein said means for selectively applying includes means for applying an output of said second filtering means to said output port when the frequency of the input signal is tuned to the frequency of the first oscillator signal, and for selectively applying a combination of the low-pass filtered output of said second filter means and the square law envelope signal to said output port during tuning.

Claim 11

A synchronous receiver as in claim 8, wherein said means for selectively applying includes one of a switch, a potentiometer and a fade-over device which selectively couples the outputs of said second filter means and said summing means to said output port to apply the envelope signal and the second mixed signal thereto, said receiver further comprising means for controlling said one of a switch, a potentiometer and a fade-over device to adjust relative amounts of the envelope signal and the second mixed signal passed through said one of a switch, a potentiometer and a fade-over device to said output port.

Claim 12

A synchronous receiver as in claim 9, wherein said one of a switch, a potentiometer and a fade-over device is a fade-over device which includes first and second controlled amplifiers having input terminals for receiving one each of the envelope signal and the second mixed signal, a summing circuit for adding together outputs of said first and second voltage amplifiers, and an invertor, said controlling means comprising means, responsive to at least one of the first and second mixed signals for providing a control signal having a level which is proportional to the coincidence of the respective frequencies of the input signal and second mixed signal, to a control terminal of said first amplifier and to an input of said invertor, said invertor having an output coupled to a control terminal of said second amplifier.

Claim 13

A synchronous receiver as in claim 7, wherein said means for selectively applying selectively applies a combination of the low-pass filtered output of said second filter means and the square law envelope signal to said output port during tuning.

Claim 14

A synchronous receiver as in claim 7, wherein said means for selectively applying includes one of a switch, a potentiometer and a fade-over device which couples the output of said second filter means to said output port.

Claim 15

A synchronous receiver as in claim 12, wherein said one of a switch, a potentiometer and a fade-over device is a fade-over device which includes first and second controlled amplifiers one of which has an input terminal for receiving the envelope signal, a summing circuit for adding together outputs of said first and second controlled amplifiers, and an invertor coupled to the a control terminal of one of the first and second controlled amplifiers.

Claim 16

A synchronous receiver as in claim 13, further comprising a recognition circuit having means for recognizing when to supply the envelope signal to and when to withhold the envelope signal from said output port, and providing a corresponding instruction signal to said fade-over device in response to which said fade-over device selectively supplies the envelope signal to or withholds the envelope signal from said output port.

Claim 17

A synchronous receiver as in claim 14, wherein said recognition circuit comprises a low-pass filter and a threshold switch connected to an output of this low-pass filter.

Claim 18

A synchronous receiver as in claim 14, wherein said recognition circuit comprises a low-pass filter, a threshold switch following the low-pass filter, a further low-pass filter coupled at an input thereof to said first phase detector, a rectifier following the further low-pass filter and an invertor following said rectifier.

Claim 19

A synchronous receiver as in claim 16, wherein the threshold switch is followed by an amplifier.

Claim 20

A synchronous receiver as in claim 17, wherein said rectifier has an output coupled to a control terminal of said amplifier.

Claim 21

A synchronous receiver as in claim 12, wherein said one of a switch, a potentiometer and a fade-over device is a switch which alternatively couples the output of said second filter means and the output of the summing means to said output port.

Claim 22

A synchronous receiver as in claim 19, further comprising means, responsive to at least one of the first and second mixed signals for controlling said switch as a function of the coincidence of the respective frequencies of the input signal and second mixed signal.

Claim 23

A synchronous receiver as in claim 7, further comprising means for forming during tuning a composite of the low-pass filtered second mixed signal and the square law envelope signal with a selected amplitude ratio of these signals and applying the composite signal to said output port.

Claim 24

A synchronous receiver as in claim 21, wherein said applying means comprises means for applying an output of said controllable amplifier to said output port, said recognition circuit comprising means for controlling said applying means with the instruction signal to adjust relative amounts of the envelope signal and the output of said controllable amplifier to said output port.

Claim 25

A synchronous receiver as in claim 21, wherein said means for applying a composite includes means for controlling the amplitude ratio in the composite signal of the low-pass filtered second mixed signal and the square law envelope signal as a function of the coincidence of the respective frequencies of the input signal and second mixed signal.

Claim 26

A synchronous receiver as in claim 7, further comprising: a recognition circuit having means for recognizing when to supply the envelope signal to and when to withhold the envelope signal from said output port, and providing a corresponding instruction signal to said means for applying in response to which said means for supplying supplies the envelope signal to or withholds the envelope signal from said output port, said recognition circuit including a one low-pass filter, a threshold switch connected to an output of this low-pass filter, an other low-pass filter coupled at an input thereof to said first phase detector, a rectifier following the other low-pass filter and an invertor following said rectifier; and a controllable amplifier which amplifies the second mixed signal, an output of said invertor controlling said controllable amplifier.

Claim 27

A synchronous receiver as in claim 24, wherein an input to said one low-pass filter is coupled to said second phase detector through said second low-pass filter means.

Claim 28

A synchronous receiver as in claim 7, further comprising a square root circuit interposed between said summing means and said output port for equalizing the envelope signal.

Claim 29

A synchronous receiver as in claim 7, further comprising: a recognition circuit having means for recognizing when to supply the envelope signal to and when to withhold the envelope signal from said output port, and providing a corresponding instruction signal to said means for applying in response to which said means for supplying supplies the envelope signal to or withholds the envelope signal from said output port, said recognition circuit including a low pass filter, a threshold switch connected to an output of this low pass filter, a recognition circuit amplifier following said threshold switch, a further low-pass filter coupled at an input thereof to said first phase detector, a rectifier following the further low-pass filter and an invertor following said rectifier; and a controllable amplifier which amplifies the second mixed signal, an output of said recognition circuit amplifier controlling said controllable amplifier.

Claim 30

A synchronous receiver as in claim 27, wherein said recognition circuit amplifier is a further controllable amplifier, an output of said invertor controlling said further controllable amplifier.