Method of and apparatus for reducing current of semiconductor memory device

Claim 2

A semiconductor memory device (1) formed on a semiconductor substrate operative in a first operating state and a second operating state, wherein said memory device (1) consumes more current in said first operating state than in said second operating state, said scmiconductor device (1) comprising: at least one memory cell for storing data; control means (11) responsive to an external control signal for controlling said memory device (1) to operate selectively in said first and second operating states; power detector means (57) for detecting an application of power to said memory device; pseudo state signal generating means (58) responsive to said power detector means (57) for generating a pseudo state signal defining said second operating state of said memory device (1); substrate bias voltage generating means (29) receiving a power for generating a bias voltage to be applied to said substrate; wherein said memory device (1) operates normally when a voltage of a prescribed level is applied to said substrate from said substrate bias voltage generating means (29), voltage establishment detector means (50, 58) detecting that the voltage generated by said substrate bias voltagc generating means (29) is established in said prescribed level; and switching means (59) responsive to said voltage establishment detector means (50, 58) for selectively applying either an externally applied control signal or a signal from said pseudo state signal generating means (58) to said control means (11), wherein said control means (11}controls said memory device (1) to operate in said second operating state in response to said applied pseudo state signal.

Claim 3

A dynamic random access memory device (1) formed on a semiconductor substrate operative in a first operating state and a second operating state, wherein said memory device (1) consumes small current in said first operating state than in said second operating state, said dynamic random access memory device (1) comprising: at least one memory cell for storing data; control means (11) responsive to an external control signal for controlling said memory device (1) to operate selcctively in said first and second operating states; power detector means (57) for detecting an application of power to said memory device (1); pseudo state signal generating means (58) responsive to said power detector means (57) for generating a pseudo state signal defining said second operating state of said memory device (1); substrate bias voltage generating means (29) receiving a power for generating a bias voltage to be applied to said substrate; wherein said memory device (1) operates normally when a voltage of a prescribed level is applied to said substrate from said substrate bias voltage generating means (29), voltage establishment detector means (50, 58) detecting that the voltage generated by said substrate bias voltage generating means (29) is established in said prescribe level; and switching means (59) responsive to said voltage establishment detector means (50, 58) for selectively applying either an externally applied control signal or a signal from said pseudo state signal generating means (58) to said control means (11), wherein said control means (11) controls said memory device (1) to operate in said second operating state in response to said applied pseudo state signal.

Claim 4

A dynamic random access memory device (1) formed on a semiconductor substrate operative in a first operating state and a second operating state, wherein said memory device (1) consumes small current in said first operating state than in said second operating state, said dynamic random access memory device (1) comprising: at least one memory cell for storing data; control means (11) responsive to an external control signal for controlling said memory device (1) to operate selcctively in said first and second operating states; power detector means (57) for detecting an application of power to said memory device (1); pseudo state signal generating means (58) responsive to said power detector means (57) for generating a pseudo state signal defining said second operating state of said memory device (1); substrate bias voltage generating means (29) receiving a power for generating a bias voltage to be applied to said substrate; wherein said memory device (1) operates normally when a voltage of a prescribed level is applied to said substrate from said substrate bias voltage generating means (29), voltage establishment detector means (50, 58) detecting that the voltage generated by said substrate bias voltage generating means (29) is established in said prescribe level; and switching means (59) responsive to said voltage establishment detector means (50, 58) for selectively applying either an externally applied control signal or a signal from said pseudo state signal generating means (58) to said control means (11), wherein said control means (11) controls said memory device (1) to operate in said second operating state in response to said applied pseudo state signal.

Claim 5

A dynamic random access memory device (1) according to claim 2, wherein said first operating state comprises an active operating state, and said second operating state comprises a standby operating state.

Claim 6

A dynamic random access memory device (1) according to claim 3, wherein said memory device (1) has a tendency to be said active operating state when power is applied for a first time.

Claim 7

A random access memory device (1) according to claim 2, wherein said substrate bias voltage generating means comprises: first oscillating means (291) generating a pulse voltage signal upon application of power; and charge pump means (292) generating said bias voltage by charging the voltage signal generated by said first oscillating means.

Claim 8

A random access memory device (1) according to claim 5, wherein said voltage establishment detector means (50) comprises first counter means connected to said first oscillating means (291) for counting pulse voltage signals generated by said first oscillating means (291), said first counter means detecting the establishment of said substrate bias voltage by counting a prescribed number of said pulse voltage signals.

Claim 9

A random access memory device (1) according to claim 2, wherein said voltage establishment detector means (50) comprises: second oscillating means (58) generating pulse voltage signals upon receipt of power; and second counter means connected to said second oscillating means (58) for counting pulse voltage signals generated by said second oscillating means (58), said second counter means detecting establishment of said substrate bias voltage by counting a prescribed number of said pulse voltage signals.

Claim 10

A random access memory device (1) according to to claim 7, wherein said voltage establishment detector means further comprises frequency dividing means (57) provided between said second oscillating means (58) and said second counter means for dividing pulse voltage signals generated by said second oscillating means (58) to apply the divided signals to said second counter means.

Claim 11

A dynamic random access memory device (1) according to claim 1, wherein said control address signal comprises at least one of a row address strobe signal and a column address strobe signal.