US4905137A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data bus control of ROM units in information processing system
Assignee: Philips North America LLC
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Filing: 1987-12-18
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Granted: 1990-02-27
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Expires: 2007-12-18
Abstract
Abstract Page-mode-organized ROMs and associated circuitry are connected only to data and control buses in an information processing system. Addressing and reading of the ROMs are controlled by a processor without connecting the ROMs to an address bus. Selection of a particular ROM and of a particular page in the selected ROM is accomplished by applying a first control signal to the control bus and a first data word to the data bus. This first data word thus serves as the address of the selected page in the selected ROM. Then a particular byte of the selected page is selected by applying a second control signal to the control bus and a second data word to the data bus. This second data word serves as the address of the selected byte. Subsequently, in response to a third control signal, the selected byte is read out of the selected ROM and applied to the data bus.
Inventors
- 👤 Gregory K. Goodhue
- 👤 William J. Price
- 👤 Ronald L. Treadway
- 👤 Brian M. Willis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:38
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623; G06F12/0215
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
382 words
An information processing system comprising means for storing information in up to 2 J pages each having up to 2 J bytes per page, where J is a positive integer, a first bus connected to said storing means, means for supplying J bits to said first bus for application to said storing means during a first cycle to select one of said pages, means for supplying J bits to said first bus for application to said storing means during a second cycle to select one of said bytes in said selected page, means for applying said selected byte from said storing means to said first bus during a third cycle, a second bus connected to said storing means, and means for supplying successive first, second and third signals to said second bus to enable said first, second and third cycles, respectively, wherein said first- and second-mentioned supplying means comprise a microprocessor, wherein said storing means comprises a page-mode-organized read-only-memory unit, an address decoder connected to said unit for selecting a particular byte on a particular page of said unit, an M-bit address latch responsive to M of the bits supplied to said first bus during said first cycle and to said first signal supplied to said second bus for applying signals to said address decoder representative of the selected one of said pages, where M is a positive integer equal to or less than J, and a J-bit address latch responsive to the J bits supplied to said first bus during said second cycle and to said second signal supplied to said second bus for applying signals to said address decoder representative of the selected one of said bytes on said selected page, wherein said applying means comprises a J-bit output buffer responsive to said third signal from said second bus and connected between said read-only-memory unit and said first bus for receiving said selected byte read out of said unit, wherein said storing means comprises N of said page-mode-organized read-only-memory units, each of said units including up to 2 M pages, where N×2 M equals 2 J , and wherein each of said units has connected thereto one of said address decoders, one of said M-bit address latches, one of said J-bit address latches and one of said J-bit output buffers.
Claim 2
Dependent Claim
382 words
An information processing system comprising means for storing information in up to 2 J pages each having up to 2 J bytes per page, where J is a positive integer, a first bus connected to said storing means, means for supplying J bits to said first bus for application to said storing means during a first cycle to select one of said pages, means for supplying J bits to said first bus for application to said storing means during a second cycle to select one of said bytes in said selected page, means for applying said selected byte from said storing means to said first bus during a third cycle, a second bus connected to said storing means, and means for supplying successive first, second and third signals to said second bus to enable said first, second and third cycles, respectively, wherein said first- and second-mentioned supplying means comprise a microprocessor, wherein said storing means comprises a page-mode-organized read-only-memory unit, an address decoder connected to said unit for selecting a particular byte on a particular page of said unit, an M-bit address latch responsive to M of the bits supplied to said first bus during said first cycle and to said first signal supplied to said second bus for applying signals to said address decoder representative of the selected one of said pages, where M is a positive integer equal to or less than J, and a J-bit address latch responsive to the J bits supplied to said first bus during said second cycle and to said second signal supplied to said second bus for applying signals to said address decoder representative of the selected one of said bytes on said selected page, wherein said applying means comprises a J-bit output buffer responsive to said third signal from said second bus and connected between said read-only-memory unit and said first bus for receiving said selected byte read out of said unit, wherein said storing means comprises N of said page-mode-organized read-only-memory units, each of said units including up to 2 M pages, where N×2 M equals 2 J , and wherein each of said units has connected thereto one of said address decoders, one of said M-bit address latches, one of said J-bit address latches and one of said J-bit output buffers.
Claim 3
Dependent Claim
74 words
A system as in claim 1 wherein each of said N units is characterized by a unique (J-M)-bit address and includes a (J-M)-bit address comparator responsive to J-M of the bits supplied to said first bus during said first cycle and to said first signal supplied to said second bus for selecting a particular one of said units for read-out when its respective characteristic address appears on said first bus during said first cycle.
Claim 4
Dependent Claim
70 words
A system as in claim 2 wherein each of said N units further includes a match latch connected to the (J-M)-bit address comparator in its respective unit and responsive to its respective comparator indicating selection of said unit for read-out by applying an ENABLE signal to its respective J-bit output buffer, whereby only the selected byte in said selected unit is applied to said first bus during said third cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-26 | 1993-08-28 | 1994-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-26 | 1997-08-28 | 1998-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-26 | 2001-08-28 | 2002-02-27 | $7700.00 | Window Closed / Lapsed |