US4904883A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit having a DC test function
Assignee: Fujitsu Semiconductor Ltd
•
Filing: 1988-12-01
•
Granted: 1990-02-27
•
Expires: 2008-12-01
Abstract
Abstract An integrated circuit receiving an input signal and producing output signal including: a set/reset circuit, operatively connected to an internal main circuit, being set in response to the first signal and reset in response to the second signal in a normal mode; an output buffer circuit, connected to the set/reset circuit, for producing the output signal in response to an output of the set/reset circuit; and a control circuit, connected between the internal main circuit and the set/reset circuit, receiving the first signal, a reset signal for initializing the internal main circuit, the first signal, the second signal, and a first test signal, during a DC test mode, the control circuit resetting the set/reset circuit in response to a receipt of the reset signal regardless of the second signal and setting the set/reset circuit in response to a receipt of the first test signal regardless of the reset signal and the first signal.
Inventors
- 👤 Hideyuki Iino
- 👤 Hidenori Hida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:17
CPC Classifications
G; G11; G11C; G11C29/00; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
177 words
An integrated circuit receiving an input signal and producing output signal comprising: an internal main circuit for carrying out various logic operations in accordance with the input signal and producing a first signal and second signal; a set/reset circuit, operatively connected to said internal main circuit, being set in response to the first signal and reset in response to the second signal in a normal mode; an output buffer circuit, connected to said set/reset circuit, for producing the output signal in response to an output of said set/reset circuit; and a control circuit, connected between said internal main circuit and said set/reset circuit, receiving the first signal, a reset signal for initializing said internal main circuit, the first signal, the second signal, and a first test signal, during a DC test mode, said control circuit resetting said set/reset circuit in response to a receipt of the reset signal regardless of the second signal and setting said set/reset circuit in response to a receipt of the first test signal regardless of the reset signal and the first signal.
Claim 2
Dependent Claim
177 words
An integrated circuit receiving an input signal and producing output signal comprising: an internal main circuit for carrying out various logic operations in accordance with the input signal and producing a first signal and second signal; a set/reset circuit, operatively connected to said internal main circuit, being set in response to the first signal and reset in response to the second signal in a normal mode; an output buffer circuit, connected to said set/reset circuit, for producing the output signal in response to an output of said set/reset circuit; and a control circuit, connected between said internal main circuit and said set/reset circuit, receiving the first signal, a reset signal for initializing said internal main circuit, the first signal, the second signal, and a first test signal, during a DC test mode, said control circuit resetting said set/reset circuit in response to a receipt of the reset signal regardless of the second signal and setting said set/reset circuit in response to a receipt of the first test signal regardless of the reset signal and the first signal.
Claim 3
Dependent Claim
34 words
An integrated circuit according to claim 1, wherein said buffer circuit comprises a three state buffer circuit, and said internal main circuit produces a gate control signal to control the three state buffer circuit.
Claim 4
Dependent Claim
68 words
An integrated circuit according to claim 2, wherein said integrated circuit further comprises a gate signal generator, connected between said internal main circuit and the three state buffer circuit, receiving the gate control signal and a second test signal and making the three state buffer in active in response to a receipt of the second test signal regardless of the gate control signal during the DC test mode.
References Cited (Backward Citations)
US4410991A
Cited
US4551841A
Cited
US4546472A
Cited
US4583041A
Cited
US4803682A
Cited
EP0202905A2
Cited
US4843592A
Cited
DE3725822A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-26 | 1993-08-28 | 1994-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-26 | 1997-08-28 | 1998-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-26 | 2001-08-28 | 2002-02-27 | $7700.00 | Window Closed / Lapsed |