Laser diode control method and circuit

Claim 2

A control method for a laser diode which comprises the steps of: providing a bias current for the laser diode; and directly determining a presettable operating point for the laser diode having a characteristic curve with a linear portion by evaluating the slope of the characteristic curve and setting the operating point at that point of the characteristic curve at which the slope is smaller than the slope in the linear portion of the characteristic curve.

Claim 3

A method as claimed in claim 1, further comprising the step of positioning the operating point at the point on the characteristic curve at which the slope is smaller by a predetermined constant factor than the slope in the linear position of the characteristic curve.

Claim 4

A method as claimed in claim 1 or 2 characterized in that the bias current is first increased, until the operating point is situated in the linear portion of the characteristic curve, and the bias current is the slightly reduced.

Claim 5

A method as claimed in claim 3, further comprising the step of controlling the light output level of the laser diode by the bias current.

Claim 6

A method as claimed in claim 1 or 2 characterized in that the laser diode, at least while the operating point is being determined, is modulated by an alternating current whose mean value is constant, and the amplitude of this alternating current is varied until the ratio of the difference between the last two amplitude values of the alternating current to the difference of the two values of the bias current before and after the control of the power output subsequent to the amplitude variation of the alternating current assumes a predetermines value.

Claim 7

A method as claimed in claim 5 characterized in that the modulation of the laser diode by an alternating current is performed by a binary pulse current having a constant duty cycle.

Claim 8

A method as claimed in claim 1 or 3, characterized in that the operating point is determined at regular time intervals while the laser diode is in operation.

Claim 9

A method as claimed in claim 1 or 2, characterized in that the intended variations of the amplitude values are gradually reduced to a minimum value.

Claim 10

A method as claimed in claim 1 or 2, characterized in that the parameters of the laser diode can be stored and provided as starting values when the laser diode is put into operation.

Claim 11

A method as claimed in claim 1 or 2, characterized in that the values of the bias current and the modulation current are compared to predetermined values and in that the predetermined values are not exceeded.

Claim 12

A method as claimed in claim 1 or 2, characterized in that the instantaneous values of bias current and modulation current are compared to predetermined maximum values and when one of these maximum values is exceeded a signal is given preventing a further increase of the relevant current value.

Claim 13

A method as claimed in claim 1 or 2, characterized in that after each variation of the modulation current the subsequent variation of the bias current is monitored, and in that a warning signal is given when a variation of the bias current exceeding the previous variation of the modulation current, fails to occur.

Claim 14

A circuit arrangement for implementing the method as claimed in claims 1 or 2, comprising a laser diode fed by at least one current source, which diode constitutes an optical coupling with a photodiode, a comparator to which is applied a proportional value for the operation of the laser diode, control logic having a first register, the first register being connected to the outputs of a bias current counter and inputs of a subtractor, and further inputs of the subtractor being connected to the outputs of the bias current counter, the output of the subtractor being connected to the inputs of a first comparator module having further inputs, said further inputs of the comparator module being connected to a series of first switches, and coupled to the first register, and the output of the first comparator module being connected to a run-off control and the latter to the bias current counter and a modulation current counter.

Claim 15

A circuit arrangement as claimed in claim 12 or 13, characterized in that at least a second register is included, which is connected to the output of one of the two counters and at least a second comparator module is included, whose first input is connected to series of second switches and whose second input is connected to the output of the counter concerned and the signal output of the second comparator module is connected to the inhibiting input of the counter concerned.

Claim 16

A circuit arrangement as claimed in claim 13 or 14, characterized in that at least a third comparator module is included, whose first input is connected to the outputs of the subtractor and whose output is connected to a warning device arrangement.

Claim 17

A circuit arrangement as claimed in claim 13 or 14, characterized in that a third register is connected to at least one of the outputs of the counter and a logic assembler is connected to the outputs of said third register and in that the outputs of this logic module are connected to the preset inputs of said counter.