US4903239A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory having a parallel input/output circuit
Assignee: NEC Corp
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Filing: 1988-03-30
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Granted: 1990-02-20
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Expires: 2008-03-30
Abstract
Abstract A memory device having improved read or write function is disclosed. The memory device comprises a memory cell array of a plurality of memory cells, a random selection circuit for reading at least one of the memory cells and a parallel read circuit coupled to a predetermined memory cells without via the random selection circuit for operatively reading the contents of the predetermined number of memory cells.
Inventors
- 👤 Yoichi Akashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:53
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1087; G11C7/1006; G11C7/1051
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
413 words
A memory circuit comprising a memory array having a plurality of word lines arranged in rows including first and second outermost rows, a plurality of digit lines arranged in columns normal to said rows, and a plurality of memory cells arranged in an array and coupled to said word plurality lines and said digit lines, each of said memory cells being coupled to only one of said word lines and including data storage means having a data node and a transfer gate having a controllable current path connected between said data node and one of said digit line and a control electrode connected to the one of said word lines to which the memory cell is connected, a row decoder coupled to said word lines for operatively selecting one of said word lines in response to row address information thereby to enable the transfer gates of the memory cells coupled to the selected word line, a column selection circuit coupled to said digit lines for operatively selecting a number of said digit lines in response to column address information for data access thereto, a number of signal lines, a parallel read-write unit coupled to said number of signal lines and to a number of memory cells in the first outermost row of said memory array corresponding to the number of signal lines, said parallel read-write unit including read-write circuits of a corresponding to the number of signal lines, each of said read-write circuits having a first node coupled to one of said signal lines and a second node directly connected to the data node of one of said cells in said first outermost row coupled to said parallel read-write unit, each of said read-write circuits transferring a signal at the first node thereof to the second node thereof in a first mode and transferring a signal at said second node to said first node in a second mode, first control means coupled to said read-write circuits for simultaneously setting said read-write circuits in said first mode thereby to simultaneously write signals on said signal lines into the storage means of said memory cells in said first outermost row coupled to said parallel read-write unit, and second control means coupled to said read-write circuits for simultaneously setting said read-write circuits in said second mode thereby to simultaneously read out to said signal lines the states of the storage means of said memory cells in said first outermost row coupled to said parallel read-write unit.
Claim 2
Dependent Claim
413 words
A memory circuit comprising a memory array having a plurality of word lines arranged in rows including first and second outermost rows, a plurality of digit lines arranged in columns normal to said rows, and a plurality of memory cells arranged in an array and coupled to said word plurality lines and said digit lines, each of said memory cells being coupled to only one of said word lines and including data storage means having a data node and a transfer gate having a controllable current path connected between said data node and one of said digit line and a control electrode connected to the one of said word lines to which the memory cell is connected, a row decoder coupled to said word lines for operatively selecting one of said word lines in response to row address information thereby to enable the transfer gates of the memory cells coupled to the selected word line, a column selection circuit coupled to said digit lines for operatively selecting a number of said digit lines in response to column address information for data access thereto, a number of signal lines, a parallel read-write unit coupled to said number of signal lines and to a number of memory cells in the first outermost row of said memory array corresponding to the number of signal lines, said parallel read-write unit including read-write circuits of a corresponding to the number of signal lines, each of said read-write circuits having a first node coupled to one of said signal lines and a second node directly connected to the data node of one of said cells in said first outermost row coupled to said parallel read-write unit, each of said read-write circuits transferring a signal at the first node thereof to the second node thereof in a first mode and transferring a signal at said second node to said first node in a second mode, first control means coupled to said read-write circuits for simultaneously setting said read-write circuits in said first mode thereby to simultaneously write signals on said signal lines into the storage means of said memory cells in said first outermost row coupled to said parallel read-write unit, and second control means coupled to said read-write circuits for simultaneously setting said read-write circuits in said second mode thereby to simultaneously read out to said signal lines the states of the storage means of said memory cells in said first outermost row coupled to said parallel read-write unit.
Claim 3
Dependent Claim
28 words
The memory circuit according to claim 1, in which the number of signal lines is larger than said number of digit lines selected by said column selection circuit.
Claim 4
Dependent Claim
21 words
The memory circuit according to claim 1, in which said column selection circuit is arranged adjacent to said second outermost row.
Claim 5
Dependent Claim
93 words
The memory circuit according to claim 1, in which each of said read-write circuits includes a NOR gate having a first input terminal coupled to the first node thereof and a second input terminal coupled to said first control means and an output terminal, a field effect transistor having a current path connected between the second node thereof and a fixed voltage terminal, a buffer having an input terminal connected to said second node and an output terminal connected to said first node and a control terminal coupled to said second control means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-19 | 1993-08-21 | 1994-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-19 | 1997-08-21 | 1998-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-19 | 2001-08-21 | 2002-02-20 | $7700.00 | Window Closed / Lapsed |