US4903005A
Expired / Lapsed
US
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Comparator circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1988-09-28
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Granted: 1990-02-20
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Expires: 2008-09-28
Abstract
Abstract A multiple digit comparator checks the first and the second input data for a match. If the two input data match, the carry input data from the previous digit is outputted as the carry output data for the next digit; if the two input data do not match, then a no match signal is outputted as the carry output data for the next digit. Next, if the carry input data and the carry output data do not match then a change point signal is outputted. When this change point signal is outputted, the first and the second input data are outputted. This facilitates the design of a more regular comparator circuit layout and of a faster comparator circuit.
Inventors
- 👤 Narumi Sakashita
- 👤 Yukihiko Shimazu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:26
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/02; G06F7/026
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
160 words
A binary one-digit comparator circuit useful for a multiple digit comparator circuit, which comprises: a match detection circuit for determining whether or not first input data and second input data match; a transmission circuit for outputting carry input data from a previous digit to a next digit if said match detection circuit determines that said first input data and said second input data match or a no match signal to said next digit if no match between said first input data and said second input data is detected; a change point detection circuit for outputting a change point signal if said carry input data and carry output data on said transmission circuit do not match; a first signal output unit for outputting said first input data when said change point detection circuit outputs said change point signal; and a second signal output unit for outputting said second input data when said change point detection circuit outputs said change point signal.
Claim 2
Dependent Claim
160 words
A binary one-digit comparator circuit useful for a multiple digit comparator circuit, which comprises: a match detection circuit for determining whether or not first input data and second input data match; a transmission circuit for outputting carry input data from a previous digit to a next digit if said match detection circuit determines that said first input data and said second input data match or a no match signal to said next digit if no match between said first input data and said second input data is detected; a change point detection circuit for outputting a change point signal if said carry input data and carry output data on said transmission circuit do not match; a first signal output unit for outputting said first input data when said change point detection circuit outputs said change point signal; and a second signal output unit for outputting said second input data when said change point detection circuit outputs said change point signal.
Claim 3
Dependent Claim
143 words
The comparator circuit of claim 1, wherein said match detection circuit comprises: a first inverter for receiving a first input data A and outputting an inverted signal; a second inverter for receiving a second input data B and outputting an inverted signal; an N channel transistor having said first input data A connected to its gate and an output of said second inverter connected to its source; an N channel transistor having an output of said first inverter connected to its gate and said second input data B connected to its source; an N channel transistor having an output of said first inverter connected to its gate and an output of said second inverter connected to its source; and an N channel transistor having said first input data A connected to its gate and said second input data B connected to its source.
Claim 4
Dependent Claim
104 words
The comparator circuit of claim 1, wherein said transmission circuit comprises: a P channel transistor having a carry input data IE connected to its source and an exclusive OR signal XOR of a first input data A and a second input data B inputted to its gate; an N channel transistor having a carry input data IE connected to its source and an exclusive NOR signal XNOR of said first input data A and said second input data B inputted to its gate; and an N channel transistor having GND connected to its source and said exclusive OR signal XOR inputted to its gate.
Claim 5
Dependent Claim
46 words
The comparator circuit of claim 1, wherein said change point detection circuit comprises: an inverter for receiving a carry output data OE and outputting an inverted signal; and an AND circuit having a carry input data IE and an output of said inverter as its inputs.
Claim 6
Dependent Claim
90 words
The comparator circuit of claim 1, wherein said first and second output units comprise respectively: an N channel transistor having a change point signal from said change point detection circuit inputted to its gate, a first input data A connected to its source, and an output signal OG connected to its drain; and an N channel transistor having a change point signal from said change point detection circuit inputted to its gate, a second input data B connected to its source, and an output signal OL connected to its drain.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-19 | 1993-08-21 | 1994-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-19 | 1997-08-21 | 1998-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-19 | 2001-08-21 | 2002-02-20 | $7700.00 | Window Closed / Lapsed |