Analog comparator

Claim 2

An analog comparator formed on an integrated circuit for comparing first voltage input to a second voltage input characterized by: at least one cascadable gain stage, the stage having an input, an output and first and second power terminals, the corresponding power terminals coupling to first and second buses, the input of the cascadable gain stage coupling to the first voltage input of the comparator; a first transistor of a first polarity type having two output terminals and an input terminal, corresponding output terminals coupling to the first bus and directly to a first voltage source, and the input terminal coupling to the second voltage input; a second transistor of a second polarity type having two output terminals and an input terminal, corresponding output terminals coupling to the second bus and directly to a second voltage source, the input terminal coupling to the second voltage input; a first current source for supplying current to the first bus; and, a second current source for supplying current to the second bus, the amount of current being substantially equal to the current supplied by the first current source; wherein the voltage of the first voltage source is different from the voltage of the second voltage source.

Claim 3

The analog comparator recited in claim 1, further comprising: at least one digital inverter responsive to the output of the cascaded gain stages.

Claim 4

The analog comparator recited in claim 2, wherein the cascadable gain stage comprises a first transistor of a first polarity and a second transistor of a second polarity, each transistor having two output terminals and an input terminal, the input terminals of the two transistors coupling together to form the input to the gain stage, two corresponding output terminals from the two transistors coupling together to form the output of the gain stage, and the remaining output terminals of the two transistors forming the corresponding first and second power terminals of the gain stage.

Claim 5

The analog comparator recited in claim 3, wherein the digital inverter is a conventional CMOS digital inverter.

Claim 6

The analog comparator recited in claim 4, wherein the first voltage source has a voltage substantially of zero volts.

Claim 7

The analog comparator recited in claim 5, wherein the second voltage input couples to a reference voltage.

Claim 8

The analog comparator recited in claim 6, wherein transistors of the first polarity type are P-channel FETs and transistors of the second polarity type are N-channel FETs.

Claim 9

An analog comparator in an integrated circuit for comparing a first voltage input to a second voltage input characterized by: at least one cascadable gain stage, the stage having an input, an output and first and second power terminals, the corresponding power terminals being coupling to first and second buses, the input of the first of the cascaded gain stages coupling to the first voltage input; a first transistor of a first polarity type having two output terminals and an input terminal, corresponding output terminals coupling to the first bus and to a node, the input terminal coupling to the second voltage input; a second transistor of a second polarity type having two output terminals and an input terminal, corresponding output terminals coupling between the second bus and the node, the input terminal coupling to the second voltage input; a current source coupling to the first bus; a subtractor having two inputs and an output, corresponding inputs coupling to the node and the second voltage input; an integrator responsive to the output of the subtractor; and, a variable current source, responsive to the integrator, for sinking current from the second bus; wherein the current supplied by the variable current source varies in response to the integrator until the voltage on the node is substantially the same as the voltage on the second voltage input.

Claim 10

An analog comparator in an integrated circuit for comparing a first voltage input to a second voltage input characterized by: at least one cascadable gain stage, the stage having an input, an output and first and second power terminals, the corresponding power terminals being coupling to first and second buses, the input of the first of the cascaded gain stages coupling to the first voltage input; a first transistor of a first polarity type having two output terminals and an input terminal, corresponding output terminals coupling to the first bus and to a node, the input terminal coupling to the second voltage input; a second transistor of a second polarity type having two output terminals and an input terminal, corresponding output terminals coupling between the second bus and the node, the input terminal coupling to the second voltage input; a current source coupling to the first bus; a subtractor having two inputs and an output, corresponding inputs coupling to the node and the second voltage input; an integrator responsive to the output of the subtractor; and, a variable current source, responsive to the integrator, for sinking current from the second bus; wherein the current supplied by the variable current source varies in response to the integrator until the voltage on the node is substantially the same as the voltage on the second voltage input.

Claim 11

The analog comparator recited in claim 8, further comprising: at least one digital inverter responsive to the output of the cascadable gain stage.

Claim 12

The analog comparator recited in claim 9, wherein the cascadable gain stage comprises a first transistor of a first polarity and a second transistor of a second polarity, each transistor having two output terminals and an input terminal, the input terminals of the two transistors coupling together to form the input to the gain stage, two corresponding output terminals from the two transistors coupling together to form the output of the gain stage, and the remaining output terminals of the two transistors forming the corresponding first and second power terminals of the gain stage.

Claim 13

The analog comparator recited in claim 10, wherein the digital inverter is a conventional CMOS digital inverter.

Claim 14

The analog comparator recited in claim 11, wherein the second voltage input couples to a reference voltage.

Claim 15

The analog comparator recited in claim 12, wherein transistors of the first polarity type are P-channel FETs and transistors of the second polarity type are N-channel FETs.

Claim 18

The method for comparing first and second voltages of claim 14, wherein the first and second buses are powered by corresponding current sources.

Claim 19

The method for comparing first and second voltages of claim 15, wherein the biasing of the first and second buses further comprises the steps of: amplifying the first voltage by a gain stage similar to a gain stage of the cascadable gain stage and powered by the first and second buses; subtracting the first voltage from the amplified first voltage to form an error voltage; and, adjusting one of the current sources in response to the error voltage until the amplified first voltage is substantially the same as the first voltage.

Claim 20

The method for comparing first and second voltages of claim 16, further comprising the step of integrating the error voltage; wherein the adjustable current source is responsive to the integrated error voltage.