US4899352A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and device to interface asynchronous apparatuses
Assignee: Alcatel Lucent Italia SpA
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Filing: 1987-09-23
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Granted: 1990-02-06
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Expires: 2007-09-23
Abstract
Abstract A system for interfacing asynchronous machines. The system includes a single-port RAM (Random Access Memory) synchronized with the master clock of only one of the asynchronous machines, and a FIFO (first in/first out) memory. The devices to implement this system consist of a single-port RAM, an FIFO memory, two counters, one of which is a write counter and the other is a read counter, a multiplexer which selects one of the two counters, and a RAM access control logic which generates the RAM control signals and the counter enabling signals and the above mentioned multiplexer select signal.
Inventors
- 👤 Silvio Cucchi
- 👤 Vittorio Corradi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:15
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/065
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
107 words
A system for interfacing asynchronous equipment operating a different clock frequencies, comprising: (a) a single-port RAM synchronized with the clock of the asynchronous equipment having the higher frequency; (b) a FIFO memory coupled to said single-port RAM; and (c) priority logic which controls read/write access to said single-port RAM from said asynchronous equipment and which, in the event of a conflict arising from simultaneous read/write requests from said asynchronous equipment, gives the request from the asynchronous equipment having a higher clock frequency priority access to said single-port RAM, the request from the asynchronous equipment having a lower clock frequency being fulfilled by read/write to said FIFO memory.
Claim 2
Independent Claim
107 words
A system for interfacing asynchronous equipment operating a different clock frequencies, comprising: (a) a single-port RAM synchronized with the clock of the asynchronous equipment having the higher frequency; (b) a FIFO memory coupled to said single-port RAM; and (c) priority logic which controls read/write access to said single-port RAM from said asynchronous equipment and which, in the event of a conflict arising from simultaneous read/write requests from said asynchronous equipment, gives the request from the asynchronous equipment having a higher clock frequency priority access to said single-port RAM, the request from the asynchronous equipment having a lower clock frequency being fulfilled by read/write to said FIFO memory.
Claim 3
Independent Claim
159 words
A system for interfacing asynchronous equipment comprising a source and a channel operating a different clock frequencies, the frequency of said source (FCKsource) being greater than the frequency of said channel (FCKchannel), said system comprising a transmit end and a receive end, each of said ends comprising: (a) a single-port RAM synchronized with the clock of said source; (b) a FIFO memory coupled to the output of said single-port RAM at the transmit end and coupled to the input of said single-port RAM at the receive end; and (c) priority logic which controls writing and reading to said single-port RAM from said source and channel based upon requests received from said source and said channel and which, in the event of a conflict arising from simultaneous read/write requests from said source and said channel, gives the request from the source priority access to said single-port RAM, the request from said channel being fulfilled by read/write to said FIFO memory.
Claim 4
Independent Claim
159 words
A system for interfacing asynchronous equipment comprising a source and a channel operating a different clock frequencies, the frequency of said source (FCKsource) being greater than the frequency of said channel (FCKchannel), said system comprising a transmit end and a receive end, each of said ends comprising: (a) a single-port RAM synchronized with the clock of said source; (b) a FIFO memory coupled to the output of said single-port RAM at the transmit end and coupled to the input of said single-port RAM at the receive end; and (c) priority logic which controls writing and reading to said single-port RAM from said source and channel based upon requests received from said source and said channel and which, in the event of a conflict arising from simultaneous read/write requests from said source and said channel, gives the request from the source priority access to said single-port RAM, the request from said channel being fulfilled by read/write to said FIFO memory.
Claim 5
Dependent Claim
26 words
A system for interfacing asynchronous equipment as recited in claim 2, wherein the following condition must be met: ##EQU4## and FSram=RAM writing frequency FLfifo=FIFO reading frequency.
Claim 6
Independent Claim
159 words
A system for interfacing asynchronous equipment comprising a source and a channel operating a different clock frequencies, the frequency of said source (FCKsource) being less than the frequency of said channel (FCKchannel), said system comprising a transmit end and a receive end, each of said ends comprising: (a) a single-port RAM synchronized with the clock of said channel; (b) a FIFO memory coupled to the input of said single-port RAM at the transmit end and coupled to the output of said single-port RAM at the receive end; and (c) priority logic which controls reading and writing to said single-port RAM from said source and said channel based upon requests received from said source and said channel and which, in the event of a conflict arising from simultaneous read/write requests from said source and channel, gives the request from the channel priority access to said single-port RAM, the request from said source being fulfilled by read/write to said FIFO memory.
Claim 7
Independent Claim
159 words
A system for interfacing asynchronous equipment comprising a source and a channel operating a different clock frequencies, the frequency of said source (FCKsource) being less than the frequency of said channel (FCKchannel), said system comprising a transmit end and a receive end, each of said ends comprising: (a) a single-port RAM synchronized with the clock of said channel; (b) a FIFO memory coupled to the input of said single-port RAM at the transmit end and coupled to the output of said single-port RAM at the receive end; and (c) priority logic which controls reading and writing to said single-port RAM from said source and said channel based upon requests received from said source and said channel and which, in the event of a conflict arising from simultaneous read/write requests from said source and channel, gives the request from the channel priority access to said single-port RAM, the request from said source being fulfilled by read/write to said FIFO memory.
Claim 8
Dependent Claim
26 words
A system for interfacing asynchronous equipment as recited in claim 4, wherein the following condition must be met: ##EQU5## and FSram=RAM writing frequency FLfifo=FIFO reading frequency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-05 | 1993-08-07 | 1994-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-05 | 1997-08-07 | 1998-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-05 | 2001-08-07 | 2002-02-06 | $7700.00 | Window Closed / Lapsed |