Linking interface system using plural controllable bidirectional bus ports for intercommunication amoung split-bus intracommunication subsystems

Claim 1

A data processing system comprising: a plurality of intracommunication bus systems, each having an address bus, a data bus, and a control bus, each address bus being assigned a unique set of addresses; a plurality of data processor components, at least one of said plurality of data processor components being connected to each of said plurality of intracommunication bus systems, having means for generating address signals over said address buses for requesting communication with any other one of said plurality of intracommunication bus systems, each of said generated address signals corresponding to one of said unique sets of addresses corresponding to a respective one of the other of the plurality of intracommunication bus systems; an intercommunication bus system having an address bus, a data bus, and a control bus, common to said plurality of intracommunication bus systems; and each of said plurality of intracommunication bus systems including a link interface means having first, second, and third bidirectional ports, each port having forward conduction, reverse conduction and non-conduction states, said ports connected respectively to corresponding data, address and control buses of said intercommunication and intracommunication bus systems to which said link interface means is connected, each said link interface means including: master control means having first controller means for selectively operating said first, second and third ports to pass address signals, data signals, and control signals through said first, second and third ports, respectively, for electrically connecting a selected one of the plurality of intracommunication bus systems to said intercommunication system in response to receipt of said address signals, said master control means including address decoder means for issuing a command signal in response to a received address signal which does not correspond to an address assigned to said corresponding intracommunication bus system from which said address signal was received, said command signal being indicative of said received address signal said first controller means including means for selecting the direction of operation of said first and third ports in response to generation of said command signal by said address decoder of the same link interface means, and means for selecting the direction of operation of said second port in response to control signals received from said control bus of said corresponding intracommunication bus system; and slave control means having second controller means for selectively operating said first, second and third ports to pass said address signals, data signals, and control signals through said first, second and third ports, respectively, for electrically connecting a selected one of the plurality of intracommunication bus systems to said intercommunication system in response to a received command signal from another link interface means when said received command signal is indicative of an address included in the unique set of addresses assigned to the intracommunication bus system associated with said link interface means.