US4896146A
Expired / Lapsed
US
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Color image processor
Assignee: Sharp Corp
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Filing: 1989-03-10
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Granted: 1990-01-23
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Expires: 2009-03-10
Abstract
Abstract A color processor which first writes each line of color data into a frame memory on the receipt of the color data from the color scanner which optically scans the color document and reads red, green, and blue components that are resolved from an individual picture element. Then, the processor reads color data before printing out the color image data via the color printer unit comprising the following elements: a memory controller, which controls the frame memory and incorporates a writing address counter and a reading address counter; an address controller which controls the writing/reading address counters; a timing circuit which controls the operations of the frame memory and the address controller by applying the predetermined drive timing; and unit for providing the timing circuit with predetermined drive timings in order that the reading of each line of color data can be synchronized with the writing of color data into the frame memory by the data-write and data-read timing clocks.
Inventors
- 👤 Masao Narumiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:40
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/46; H04N1/56; H04N1/40; H04N1/64; H04N1/648; H04N2201/00; H04N2201/32; H04N2201/3285; H04N2201/3287
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
162 words
A color image processor for synchronously writing color data into a frame memory and reading said color data from said frame memory comprising: color scanning means for sequentially scanning a plurality of lines of color data from a color document; timing control means for developing a data timing signal in response to an external write signal and an external read signal; writing address controlling means for writing each line of said plurality of lines of color data from said color scanning means, in synchronism with said data timing signal, at a plurality of addresses in said frame memory by generating said plurality of addresses for each line of said plurality of lines; and reading address controlling means for generating said plurality of addresses for reading said plurality of lines of color data from said frame memory in synchronism with said data timing signal in response to a predetermined number of lines of said plurality of lines being written into said frame memory.
Claim 2
Dependent Claim
162 words
A color image processor for synchronously writing color data into a frame memory and reading said color data from said frame memory comprising: color scanning means for sequentially scanning a plurality of lines of color data from a color document; timing control means for developing a data timing signal in response to an external write signal and an external read signal; writing address controlling means for writing each line of said plurality of lines of color data from said color scanning means, in synchronism with said data timing signal, at a plurality of addresses in said frame memory by generating said plurality of addresses for each line of said plurality of lines; and reading address controlling means for generating said plurality of addresses for reading said plurality of lines of color data from said frame memory in synchronism with said data timing signal in response to a predetermined number of lines of said plurality of lines being written into said frame memory.
Claim 3
Dependent Claim
15 words
The color image processor of claim 1, wherein said frame memory is a dynamic RAM.
Claim 4
Dependent Claim
18 words
The color image processor of claim 1, wherein said frame memory comprises first, second and third memory components.
Claim 5
Dependent Claim
35 words
The image processor of claim 3, wherein said first memory component is a red memory component, said second memory component is a green memory component and said third memory component is a blue memory component.
Claim 6
Dependent Claim
31 words
The image processor of claim 1, wherein each line of said plurality of lines of color data comprises a red data component, a green data component and a blue data component.
Claim 7
Dependent Claim
34 words
The image processor of claim 1, wherein said timing means comprises timing synchronization means and refresh time decision means for generating said data timing and read signals in response to said external write signal.
Claim 8
Dependent Claim
34 words
The image processor of claim 1, wherein said writing address controlling means comprises a writing address counter for selecting said addresses in said frame memory for writing each line of said plurality of lines.
Claim 9
Dependent Claim
31 words
The image processor of claim 1, wherein said reading address controlling means comprises a reading address counter for determining said addresses for reading said plurality of lines from said frame memory.
Claim 10
Independent Claim
160 words
A method for synchronously writing color data into a frame memory and reading said color data from said frame memory in a color image processor comprising the steps of: sequentially scanning a plurality of lines of color data from a color document by color scanning means; developing a data timing signal in response to an external write signal and an external read signal by timing control means; writing each line of said plurality of lines of color data from said color scanning means in synchronism with said data timing signal at a plurality of addresses in said frame memory by generating said plurality of lines by writing address controlling means; and generating said plurality of addresses for reading said plurality of lines of color data from said frame memory in synchronism with said data time signal in response to a predetermined number of lines of said plurality of lines being written into said frame memory by reading address controlling means.
Claim 11
Independent Claim
160 words
A method for synchronously writing color data into a frame memory and reading said color data from said frame memory in a color image processor comprising the steps of: sequentially scanning a plurality of lines of color data from a color document by color scanning means; developing a data timing signal in response to an external write signal and an external read signal by timing control means; writing each line of said plurality of lines of color data from said color scanning means in synchronism with said data timing signal at a plurality of addresses in said frame memory by generating said plurality of lines by writing address controlling means; and generating said plurality of addresses for reading said plurality of lines of color data from said frame memory in synchronism with said data time signal in response to a predetermined number of lines of said plurality of lines being written into said frame memory by reading address controlling means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-22 | 1993-07-24 | 1994-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-22 | 1997-07-24 | 1998-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-22 | 2001-07-24 | 2002-01-23 | $7700.00 | Window Closed / Lapsed |