Compact, real time tape drive system

Claim 2

An error detection and correction system for nine track tape recorders comprising: means for receiving successive bytes of digital information each including eight bits; means for calculating a parity correction bit for each said byte of data and adding it to said eight bits to form a series of nine bit bytes of binary information; a microcomputer; means for forming a cyclic redundancy code for a block of data bytes, in the form of an error correction check byte, by offsetting successive bytes in said block of data bytes by one bit, and adding the digital data, to obtain a product high and a product low, using the address indicated by the product high as a pointer to retrieve a Modifier from a stored table associated with the microcomputer, and adding the modifier to the product low to form an error correction check (ECC) byte; means for recording the block of data bytes along with the ECC byte on a nine track tape; means for retrieving the block of data and ECC byte from the tape; means for calculating a parity check error vector by checking the parity of each byte in the block of data and the ECC byte; means for calculating the error syndrome by repeating the steps for forming the ECC byte, but including the ECC byte; means for identifying two of the nine columns or tracks Ei and Ej which most probably contain errors; means for calculating the error correction vectors for each of columns Ei and Ej, using the error vector, the error syndrome, an identification of the two channels Ei and Ej, and Look-Up Tables stored in memory associated with said microcomputer; and means for supplying the disrupted data to an error correction circuit concurrently with data representing the error correction vectors, to correct the disrupted data to its input format.

Claim 3

A system as defined in claim 1 wherein said system includes means for correcting errors on a real-time, on-line basis.

Claim 4

A system as defined in claim 1 wherein said system includes means for performing the offset multiplication and addition algorithm as set forth in claim 1 at least three times.

Claim 5

A system as defined in claim 1 wherein said means for calculating error correction vectors includes digital storage containing the Modifier Table; a Y Table having as its input the error vector, a K Table having as its input the Ei and Ej column identifications; means for combining the output from the Y Table with the error syndrome to form a vector/syndrome value; means for multiplying the Vector Syndrome Value by the output from the K Table to yield a first column error vector; and means for combining the parity error vector with said first column error vector to provide the second column error vector.

Claim 6

A system as defined in claim 4 wherein said Y Table is a composite table which includes two subtables, a V Table and a XiV Table, and wherein the output from the V Table is incremented by the number of the Ei channel to provide a pointer or address to the XiV Table, yielding the desired output from the composite Y Table.

Claim 7

A system as defined in claim 1 wherein said means for calculating the error correction vectors includes a digital signal processor and associated read only memories in which said tables are stored.

Claim 8

A system as defined in claim 6 wherein means are provided for operating said digital signal processor at a speed which is many times faster than the rate at which information is retrieved from said tape.

Claim 9

A system as defined in claim 7 including input buffer means for receiving possibly disrupted data from said tape and output buffer means for storing corrected output data prior to transmitting it to an associated host computer.

Claim 10

An error detection and correction system for parallel words of binary information employing a feedback shift register type of error correction checking scheme, comprising: means for receiving successive words of digital information each including at least several bits and forming a block of data; means for calculating a parity correction bit for each said word of data and adding it to said word to form a series of longer words of binary information; a microcomputer; means for forming an error correction check (ECC) word conforming to said error correction checking scheme; means for transmitting said data including said ECC check word so that some of said data may be disrupted; means for retrieving the block of data and the ECC word; means for calculating a parity check error vector by checking the parity of each word in the block of data and the ECC word; means for calculating the error syndrome by offsetting successive words in said block of data words and said ECC word, by one bit, and adding the digital data, to obtain a product high and a product low, using the address indicated by the product high as a pointer to retrieve a Modifier from a stored table associated with the microcomputer, and adding the Modifier to the product low to form an error correction syndrome; means for identifying two of the word bit positions or channels Ei and Ej which most probably contain errors; means for calculating the error correction vectors for each of channels Ei and Ej, using the parity check error vector, the error syndrome, an identification of the two channels Ei and Ej, and Look-Up Tables stored in memory associated with said microcomputer; and means for supplying the disrupted data to an error correction circuit concurrently with data representing the error correction vectors, to correct the disrupted data to its input format.

Claim 11

An error detection and correction system for parallel words of binary information employing a feedback shift register type of error correction checking scheme, comprising: means for receiving successive words of digital information each including at least several bits and forming a block of data; means for calculating a parity correction bit for each said word of data and adding it to said word to form a series of longer words of binary information; a microcomputer; means for forming an error correction check (ECC) word conforming to said error correction checking scheme; means for transmitting said data including said ECC check word so that some of said data may be disrupted; means for retrieving the block of data and the ECC word; means for calculating a parity check error vector by checking the parity of each word in the block of data and the ECC word; means for calculating the error syndrome by offsetting successive words in said block of data words and said ECC word, by one bit, and adding the digital data, to obtain a product high and a product low, using the address indicated by the product high as a pointer to retrieve a Modifier from a stored table associated with the microcomputer, and adding the Modifier to the product low to form an error correction syndrome; means for identifying two of the word bit positions or channels Ei and Ej which most probably contain errors; means for calculating the error correction vectors for each of channels Ei and Ej, using the parity check error vector, the error syndrome, an identification of the two channels Ei and Ej, and Look-Up Tables stored in memory associated with said microcomputer; and means for supplying the disrupted data to an error correction circuit concurrently with data representing the error correction vectors, to correct the disrupted data to its input format.

Claim 12

A system as defined in claim 9 wherein said means for calculating error correction vectors includes digital storage containing the Modifier Table; a Y Table having as its input the error vector, a K Table having as its input the Ei and Ej channel identifications; means for combining the output from the Y Table with the error syndrome to form a vector/syndrome value; means for multiplying the Vector Syndrome Value by the output from the K Table to yield a first channel error vector; and means for combining the parity error vector with said first channel error vector to provide the second channel error vector.

Claim 13

A system as defined in claim 9 wherein said system includes means for correcting errors on a real-time, on-line basis.

Claim 14

An error detection and correction method for nine track tape recorders comprising: receiving successive bytes of digital information each including eight bits; calculating a parity correction bit for each said byte of data and adding it to said eight bits to form a series of nine bit bytes of binary information; forming a cyclic redundancy code for a block of data bytes, in the form of an error correction check byte, by offsetting successive bytes in said block of data bytes by one bit, and adding the digital data, to obtain a product high and a product low, using the address indicated by the product high as a pointer to retrieve a Modifier from a stored table associated with the microcomputer, and adding the modifier to the product low to form an error correction check (ECC) byte; recording the block of data bytes along with the ECC byte on a nine track tape; retrieving the block of data and ECC byte from the tape; calculating a parity check error vector by checking the parity of each byte in the block of data and the ECC byte; calculating the error syndrome by repeating the steps for forming the ECC byte, but including the ECC byte; identifying two of the nine columns or tracks Ei and Ej which most probably contain errors; calculating the error correction vectors for each of columns Ei and Ej, using the error vector, the error syndrome, the parity check error vector, and stored Look-Up Tables; and supplying the disrupted data to an error correction circuit concurrently with data representing the error correction vectors, to correct the disrupted data to its input format.

Claim 15

An error detection and correction method for nine track tape recorders comprising: receiving successive bytes of digital information each including eight bits; calculating a parity correction bit for each said byte of data and adding it to said eight bits to form a series of nine bit bytes of binary information; forming a cyclic redundancy code for a block of data bytes, in the form of an error correction check byte, by offsetting successive bytes in said block of data bytes by one bit, and adding the digital data, to obtain a product high and a product low, using the address indicated by the product high as a pointer to retrieve a Modifier from a stored table associated with the microcomputer, and adding the modifier to the product low to form an error correction check (ECC) byte; recording the block of data bytes along with the ECC byte on a nine track tape; retrieving the block of data and ECC byte from the tape; calculating a parity check error vector by checking the parity of each byte in the block of data and the ECC byte; calculating the error syndrome by repeating the steps for forming the ECC byte, but including the ECC byte; identifying two of the nine columns or tracks Ei and Ej which most probably contain errors; calculating the error correction vectors for each of columns Ei and Ej, using the error vector, the error syndrome, the parity check error vector, and stored Look-Up Tables; and supplying the disrupted data to an error correction circuit concurrently with data representing the error correction vectors, to correct the disrupted data to its input format.

Claim 16

A method as defined in claim 12 wherein the calculating of the error correction vectors includes using the modifier Table; a Y Table having as its input the error vector, a K Table having as its input the Ei and Ej column identifications; combining the output from the Y Table with the error syndrome to form a vector/syndrome value; multiplying the Vector Syndrome Value by the output from the K Table to yield a first column error vector; and combining the parity error vector with said first column error vector to provide the second column error vector.

Claim 17

A method as defined in claim 12 wherein correction of errors is accomplished on a real-time, on-line basis.

Claim 18

An error detection and correction system for parallel bytes of information employing a feedback shift register type of error correction checking scheme, comprising: means for receiving successive bytes of digital information each including eight bits; a microcomputer; means for forming a cyclic redundancy code for a block of data bytes, in the form of an error correction check byte, by offsetting successive bytes in said block of data bytes by one bit, and adding the digital data, to obtain a product high and a product low, using the address indicated by the product high as a pointer to retrieve a Modifier from a stored table associated with the microcomputer, and adding the modifier to the product low to form an error correction check (ECC) byte, conforming to said error correction checking scheme; means for calculating parity correction bits for selected bits of said data and adding them to said bytes of data to form an enlarged block of data; means for transmitting said data so that some of said data may be disrupted; means for retrieving the block of transmitted data; means for calculating a parity check error vector by checking the parity of each parity check bit in the block of data; means for calculating the error syndrome by repeating the steps for forming the ECC byte, and combining the result of that process with the ECC byte; means for identifying two of the nine columns or tracks Ei and Ej which most probably contain errors; means for calculating the error correction vectors for each of columns Ei and Ej, using the parity check error vector, the error syndrome, an identification of the two channels Ei and Ej, and Look-Up Tables stored in memory associated with said microcomputer; and means for supplying the disrupted data to an error correction circuit concurrently with data representing the error correction vectors, to correct the disrupted data to its input format.

Claim 19

An error detection and correction system for parallel bytes of information employing a feedback shift register type of error correction checking scheme, comprising: means for receiving successive bytes of digital information each including eight bits; a microcomputer; means for forming a cyclic redundancy code for a block of data bytes, in the form of an error correction check byte, by offsetting successive bytes in said block of data bytes by one bit, and adding the digital data, to obtain a product high and a product low, using the address indicated by the product high as a pointer to retrieve a Modifier from a stored table associated with the microcomputer, and adding the modifier to the product low to form an error correction check (ECC) byte, conforming to said error correction checking scheme; means for calculating parity correction bits for selected bits of said data and adding them to said bytes of data to form an enlarged block of data; means for transmitting said data so that some of said data may be disrupted; means for retrieving the block of transmitted data; means for calculating a parity check error vector by checking the parity of each parity check bit in the block of data; means for calculating the error syndrome by repeating the steps for forming the ECC byte, and combining the result of that process with the ECC byte; means for identifying two of the nine columns or tracks Ei and Ej which most probably contain errors; means for calculating the error correction vectors for each of columns Ei and Ej, using the parity check error vector, the error syndrome, an identification of the two channels Ei and Ej, and Look-Up Tables stored in memory associated with said microcomputer; and means for supplying the disrupted data to an error correction circuit concurrently with data representing the error correction vectors, to correct the disrupted data to its input format.

Claim 20

A system as defined in claim 15 wherein said means for calculating error correction vectors includes digital storage containing the Modifier Table; a Y Table having as its input the error vector, a K Table having as its input the Ei and Ej column identifications; means for combining the output from the Y Table with the error syndrome to form a vector/syndrome value; means for multiplying the Vector Syndrome Value by the output from the K Table to yield a first Ei column error vector; and means for combining the parity error vector with said first Ei column error vector to provide the second Ei column error vector.

Claim 21

A system as defined in claim 15 wherein said system includes means for correcting errors on a real-time, on-line basis.

Claim 22

A system as defined in claim 15 wherein said means for calculating the error correction vectors includes a digital signal processor and associated read only memories in which said tables are stored.

Claim 23

A system as defined in claim 18 wherein means are provided for operating said digital signal processor at a speed which is many times faster than the rate at which information is retrieved from said tape.

Claim 24

An error detection and correction method for nine track tape recorders comprising: receiving successive bytes of digital information each including eight bits; calculating a parity correction bit for each said byte of data and adding it to said eight bits to form a series of nine bit bytes of binary information; forming a cyclic redundancy code for a block of data bytes, in the form of an error correction check byte, by offsetting successive bytes in said block of data bytes by one bit, and adding the digital data, to obtain a product high and a product low, using the address indicated by the product high as a pointer to retrieve a Modifier from a stored table associated with the microcomputer, and adding the Modifier to the product low to form an error correction check (ECC) byte; transmitting the block of data bytes along with the ECC byte so that some of the data may be disrupted; retrieving the block of data and ECC byte; calculating a parity check error vector by checking the parity of each byte in the block of data and the ECC byte; calculating the error syndrome by repeating the steps for forming the ECC byte, and combining the result of that process with the ECC byte; identifying two of the nine columns or tracks Ei and Ej which most probably contain errors; calculating the error correction vectors for each of columns Ei and Ej, using the parity check error vector, the error syndrome, an identification of columns Ei and Ej, and stored Look-Up Tables; and supplying the disrupted data to an error correction circuit concurrently with data representing the error correction vectors, to correct the disrupted data to its input format.

Claim 25

An error detection and correction method for nine track tape recorders comprising: receiving successive bytes of digital information each including eight bits; calculating a parity correction bit for each said byte of data and adding it to said eight bits to form a series of nine bit bytes of binary information; forming a cyclic redundancy code for a block of data bytes, in the form of an error correction check byte, by offsetting successive bytes in said block of data bytes by one bit, and adding the digital data, to obtain a product high and a product low, using the address indicated by the product high as a pointer to retrieve a Modifier from a stored table associated with the microcomputer, and adding the Modifier to the product low to form an error correction check (ECC) byte; transmitting the block of data bytes along with the ECC byte so that some of the data may be disrupted; retrieving the block of data and ECC byte; calculating a parity check error vector by checking the parity of each byte in the block of data and the ECC byte; calculating the error syndrome by repeating the steps for forming the ECC byte, and combining the result of that process with the ECC byte; identifying two of the nine columns or tracks Ei and Ej which most probably contain errors; calculating the error correction vectors for each of columns Ei and Ej, using the parity check error vector, the error syndrome, an identification of columns Ei and Ej, and stored Look-Up Tables; and supplying the disrupted data to an error correction circuit concurrently with data representing the error correction vectors, to correct the disrupted data to its input format.