US4893155A
Expired / Lapsed
US
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Heterojunction field effect transistor device and process of fabrication thereof
Assignee: NEC Corp
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Filing: 1988-05-16
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Granted: 1990-01-09
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Expires: 2008-05-16
Abstract
Abstract For improvement in a transit time of electrons, there is disclosed a heterojunction field effect transistor fabricated on a semi-insulating GaAs substrate, comprising a first layer overlying the semi-insulating substrate and formed of a high-purity GaAs, a second layer overlying the first layer and formed of an n-type AlGaAs which is smaller in electron affinity than the high-purity GaAs, a source region penetrating from the first layer into the second layer so as to be in contact with the active channel layer formed in the first layer and formed of an gallium-rich AlGaAs, a drain region, and a gate electrode formed on the second layer, an energy gap takes place between the source region and the first layer due to a lower edge of the conduction band thereof higher in energy level than that of the high-purity GaAs, thereby accelerating electrons supplied from the source region to the active channel layer.
Inventors
- 👤 Keiichi Ohata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:29
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/051; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/80; H10D62/82; H10D62/824; Y; Y10; Y10S; Y10S148/00; Y10S148/029; Y10S148/072; Y10S148/169
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
312 words
A heterojunction field effect transistor fabricated on a semi-insulating substrate, comprising: (a) a first layer overlying said semi-insulating substrate and formed of a first high-purity compound semiconductor material, said first layer having a lower portion, an upper portion and a first shoulder portion interconnecting the lower and upper portions; (b) a second layer topographically overlying said first layer so that a step configuration of said first shoulder portion is transferred to said second layer to form lower and upper portions formed of a second compound semiconductor material and a second shoulder portion interconnecting the lower and upper portions and formed of a fourth compound semiconductor material, said second compound semiconductor material being smaller in electron affinity than said first high-purity compound semiconductor material, said fourth compound semiconductor material being smaller in electron affinity than said first high-purity compound semiconductor material but larger in electron affinity than said second compound semiconductor material, an active channel layer taking place in said upper portion of said first layer along a heterojunction formed between said first layer and said second layer; (c) a source contact region formed on the lower portion of said second layer so as to be in contact with said second shoulder portion, said source contact region being formed of a third compound semiconductor material; (d) a drain region formed on the upper portion of said second layer so as to be electrically coupled to said active channel layer, said drain region being spaced from said source region; and (e) a gate electrode formed on the upper portion of said second layer, said gate electrode being biased to control said active channel layer, wherein said fourth compound semiconductor material has a lower edge of a conduction band higher in energy level than that of said first high-purity compound semiconductor material but lower in energy level than that of said second compound semiconductor material.
Claim 2
Dependent Claim
312 words
A heterojunction field effect transistor fabricated on a semi-insulating substrate, comprising: (a) a first layer overlying said semi-insulating substrate and formed of a first high-purity compound semiconductor material, said first layer having a lower portion, an upper portion and a first shoulder portion interconnecting the lower and upper portions; (b) a second layer topographically overlying said first layer so that a step configuration of said first shoulder portion is transferred to said second layer to form lower and upper portions formed of a second compound semiconductor material and a second shoulder portion interconnecting the lower and upper portions and formed of a fourth compound semiconductor material, said second compound semiconductor material being smaller in electron affinity than said first high-purity compound semiconductor material, said fourth compound semiconductor material being smaller in electron affinity than said first high-purity compound semiconductor material but larger in electron affinity than said second compound semiconductor material, an active channel layer taking place in said upper portion of said first layer along a heterojunction formed between said first layer and said second layer; (c) a source contact region formed on the lower portion of said second layer so as to be in contact with said second shoulder portion, said source contact region being formed of a third compound semiconductor material; (d) a drain region formed on the upper portion of said second layer so as to be electrically coupled to said active channel layer, said drain region being spaced from said source region; and (e) a gate electrode formed on the upper portion of said second layer, said gate electrode being biased to control said active channel layer, wherein said fourth compound semiconductor material has a lower edge of a conduction band higher in energy level than that of said first high-purity compound semiconductor material but lower in energy level than that of said second compound semiconductor material.
Claim 3
Dependent Claim
21 words
A heterojunction field effect transistor as set forth in claim 1, in which said first layer is formed of undoped gallium-arsenide.
Claim 4
Dependent Claim
65 words
A heterojunction field effect transistor as set forth in claim 2, in which said second compound semiconductor material is formed of n-type aluminum-gallium-arsenide represented by Al x1 Ga 1-x1 As where x1 ranges between about 0.1 and about 0.5, and in which said fourth compound semiconductor material is formed of n-type aluminum-gallium-arsenide having an aluminum content less than that of said second compound semiconductor material.
Claim 5
Dependent Claim
38 words
A heterojunction field effect transistor as set forth in claim 3, in which said fourth region is formed of heavily-doped n-type aluminum-gallium-arsenide represented by Al x2 Ga 1-x2 As where x2 ranges between about 0.02 and about 0.40.
Claim 6
Dependent Claim
24 words
A heterojunction field effect transistor as set forth in claim 4, in which said gate electrode is smaller in length than about 1.0 micron.
References Cited (Backward Citations)
US4593301A
Cited
JPS61187373A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-08 | 1993-07-10 | 1994-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-08 | 1997-07-10 | 1998-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-08 | 2001-07-10 | 2002-01-09 | $7700.00 | Window Closed / Lapsed |