US4893033A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable logic array having input transition detection for generating precharge
Assignee: Fujitsu VLSI Ltd
•
Filing: 1988-10-05
•
Granted: 1990-01-09
•
Expires: 2008-10-05
Abstract
Abstract A programmable logic array circuit includes a pulse signal generating circuit for generating a pulse signal by detecting a change in levels of input signals. A first transistor for precharging a product term line is provided. A second transistor is provided for discharging an OR array input line. A third transistor is provided for precharging an OR array output line. The first through third transistors are controlled by the pulse signal. In other words, the first through third transistors are controlled in response to the signal change of the input signals. In order to facilitate the discharging operation with respect to the OR array input line, a fourth transistor may be provided on a side opposite to the second transistor.
Inventors
- 👤 Kiyoshi Itano
- 👤 Kohji Shimbayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:01
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
197 words
A programmable logic array circuit comprising: an AND array comprising a plurality of memory cells connected to input lines and product term lines, input signals being supplied to the AND array through the input lines; an OR array comprising a plurality of memory cells connected to OR array input lines and OR array output lines, output signals being extracted through the OR array output lines; pulse signal generating means for generating a pulse signal by detecting a change in levels of the input signals; product term sensing buffer means for sensing levels of the product term lines, sensed levels being sent to the OR array through the OR array input lines, the product term sensing buffer means comprising first precharging means for charging the product term lines up to a predetermined potential in response to the pulse signal derived from the pulse signal generating means, and discharging means for discharging the OR array input lines in response to the pulse signal derived from the pulse signal generating means; and second precharging means for charging the OR array input lines up to a predetermined potential in response to the pulse signal derived from the pulse signal generating means.
Claim 2
Dependent Claim
197 words
A programmable logic array circuit comprising: an AND array comprising a plurality of memory cells connected to input lines and product term lines, input signals being supplied to the AND array through the input lines; an OR array comprising a plurality of memory cells connected to OR array input lines and OR array output lines, output signals being extracted through the OR array output lines; pulse signal generating means for generating a pulse signal by detecting a change in levels of the input signals; product term sensing buffer means for sensing levels of the product term lines, sensed levels being sent to the OR array through the OR array input lines, the product term sensing buffer means comprising first precharging means for charging the product term lines up to a predetermined potential in response to the pulse signal derived from the pulse signal generating means, and discharging means for discharging the OR array input lines in response to the pulse signal derived from the pulse signal generating means; and second precharging means for charging the OR array input lines up to a predetermined potential in response to the pulse signal derived from the pulse signal generating means.
Claim 3
Dependent Claim
50 words
A programmable logic array circuit as claimed in claim 1, further comprising second discharging means for discharging the OR array input lines in response to the pulse signal derived from the pulse signal generating means, in addition to the first discharging means provided included in the product term sensing buffer.
Claim 4
Dependent Claim
61 words
A programmable logic array circuit as claimed in claim 2, wherein each of the first and second precharging means comprises a metal oxide semiconductor (MOS) transistor, wherein each of the first and second discharging means comprises a MOS transistor, and wherein gates of the MOS transistors of the first and second precharging and discharging means are supplied with the pulse signal.
Claim 5
Dependent Claim
84 words
A programmable logic array circuit as claimed in claim 2, wherein the pulse signal generating means generates the pulse signal which consists of a first pulse signal and a second pulse signal, and wherein the first pulse signal is a low-active signal, and wherein the second pulse signal corresponds to a pulse signal obtained by inverting the first pulse signal, and wherein either one of the first and second pulse signals is supplied to each of the first and second precharging and discharging means.
Claim 6
Dependent Claim
82 words
A programmable logic array circuit as claimed in claim 4, wherein the first precharging means comprises an n-channel MOS transistor provided for each of the product term lines, and the first discharging means comprises a p-channel MOS transistor provided for each of the OR array input lines, and wherein the first pulse signal is supplied to the gate of the n-channel MOS transistor of the first precharging means and to the gate of the p-channel MOS transistor of the first discharging means.
Claim 7
Dependent Claim
71 words
A programmable logic array circuit as claimed in claim 4, wherein the second precharging means comprises an n-channel MOS transistor provided for each of the OR array output lines, and the second discharging means comprises an n-channel MOS transistor provided for each of the OR array input lines, and wherein the second pulse signal is supplied to the gates of the n-channel MOS transistors of the second precharging and discharging means.
Claim 8
Dependent Claim
45 words
A programmable logic array circuit as claimed in claim 2, wherein the second discharging means is located at an end of the OR array input lines opposite to an end where the product term sensing buffer means is connected to the OR array input lines.
Claim 9
Dependent Claim
86 words
A programmable logic array circuit as claimed in claim 4, wherein the pulse signal generating means comprises detecting means provided for each of the input signals for detecting a change in levels of the input signals; an OR circuit for receiving all the output signals of the detecting means, an output signal of the OR circuit being the second pulse signal; and an inverter circuit for inverting the output signal of the OR circuit, an output signal of the inverter circuit being the first pulse signal.
Claim 10
Dependent Claim
42 words
A programmable logic array circuit as claimed in claim 1, further comprising a first pull-up means for pulling the product term lines to the predetermined potential, and a second pull-up means for pulling the OR array output lines to the predetermined potential.
Claim 11
Dependent Claim
142 words
A programmable logic array circuit as claimed in claim 8, wherein the detecting means comprises first and second inverter circuits which are cascade-connected; third and fourth inverter circuits each being connected to an output terminal of the second inverter circuit; fifth inverter circuit being connected to an output terminal of the third inverter circuit; and first and second MOS transistors for controlling the fourth and fifth inverter circuits, respectively, and wherein a gate of the first MOS transistor is connected to an output terminal of the fifth inverter circuit, and a gate of the second MOS transistor is connected to an output of the fourth inverter circuit, and wherein the detecting means further comprises an NAND circuit connected to the output terminals of the fourth and fifth inverter circuits; and an inverter circuit connected to an output terminal of the NAND circuit.
Claim 12
Dependent Claim
102 words
A programmable logic array circuit as claimed in claim 2, wherein the pulse signal generating means generates the pulse signal which consists of first, second, third and fourth pulse signals, and wherein the first and second pulse signals are low-active signals, and wherein a trailing edge of each of the second, third and fourth pulse signals lags behind a trailing edge of the first pulse signal, and wherein the first and second pulse signals are supplied to the first precharging and discharging means, respectively, and wherein the third and fourth pulse signals are supplied to the second discharging and precharging means, respectively.
Claim 13
Dependent Claim
117 words
A programmable logic array circuit as claimed in claim 11, wherein the pulse signal generating means comprises detecting means provided for each of the input signals for detecting a change in levels of the input signals; a NOR circuit for receiving all the output signals of the detecting means, an output signal of the NOR circuit being the first pulse signal; a first inverter circuit for inverting the output signal of the NOR circuit, an output signal of the first inverter circuit being the third and fourth pulse signals; and a second inverter circuit for inverting the output signal of the first inverter circuit, an output signal of the second inverter circuit being the second pulse signal.
Claim 14
Dependent Claim
65 words
A programmable logic array circuit as claimed in claim 12, wherein the pulse signal generating means comprises a buffer circuit composed of two cascaded inverters, and wherein first pulse signal derived from the NOR circuit is supplied to an input of the buffer circuit, so that an output signal of the buffer circuit is supplied to the first precharging means as the first pulse signal.
References Cited (Backward Citations)
JPS5161257A
Cited
JPS5161256A
Cited
US4577190A
Cited
US4740721A
Cited
JPS62190926A
Cited
US4697105A
Cited
US4769562A
Cited
US4839539A
Cited
US4760290A
Cited
US4831285A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-08 | 1993-07-10 | 1994-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-08 | 1997-07-10 | 1998-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-08 | 2001-07-10 | 2002-01-09 | $7700.00 | Window Closed / Lapsed |