Spindle motor control system for magnetic disk apparatus

Claim 2

A spindle motor control system for a magnetic disk apparatus comprising a magnetic disk unit which outputs an index signal upon rotation of a spindle motor therein and inputs a control signal for controlling a rotation of the spindle motor by the control signal, and control means for inputting the index signal from said magnetic disk unit to output the control signal to said magnetic disk unit, said control means comprising means for generating a master clock signal of a predetermined frequency; means for frequency-dividing the master clock signal to generate a plurality of frequency-divided signals; means for generating a master index signal upon each rotation of said spindle motor by frequency dividing one of the plurality of frequency-divided signals; detector means for detecting a time interval between the master index signal and the index signal to output a phase control signal and a select signal; selector means for selecting and outputting one of the plurality of frequency-divided signals from said frequency-dividing means in accordance with the select signal; means for masking the master clock signal for a time period in accordance with the phase control signal, the master index signal, and an output signal of said selector means to output the control signal to said magnetic disk unit.

Claim 3

A spindle motor control system for a magnetic disk apparatus comprising: at least one magnetic disk unit which includes a spindle motor for driving a magnetic disk and outputs an index signal upon rotation of said spindle motor and controlling rotation of said spindle motor by a clock signal; and control means for controlling said at least one magnetic disk unit, said control means comprising: a frequency generator for generating a master clock signal of a predetermined frequency; a first frequency divider for frequency-dividing the master clock signal from said frequency generator by 2 1 , 2 2 , . . . , 2 N ; a second frequency divider for frequency-dividing the signal frequency-divided by 2 n to generate a master index signal upon each rotation of said spindle motor; a time interval detector for detecting a time interval between the master index signal and the index signal output from said at least one magnetic disk unit and outputting a phase control signal and a select signal corresponding to the detected time interval; a data selector for selecting and outputting one of the signals frequency-divided by 2 1 , 2 2 , . . . , 2 N in accordance with the select signal; a clock window circuit for masking the master clock signal from said frequency generator for a time period in accordance with the phase control signal, the master index signal, and an output signal of said data selector; and a third frequency divider for frequency-dividing the output signal from said clock window circuit and supplying the frequency-divided signal as the clock signal to said at least one magnetic disk unit.

Claim 4

A spindle motor control system for a magnetic disk apparatus comprising: at least one magnetic disk unit which includes a spindle motor for driving a magnetic disk and outputs an index signal upon rotation of said spindle motor and controlling rotation of said spindle motor by a clock signal; and control means for controlling said at least one magnetic disk unit, said control means comprising: a frequency generator for generating a master clock signal of a predetermined frequency; a first frequency divider for frequency-dividing the master clock signal from said frequency generator by 2 1 , 2 2 , . . . , 2 N ; a second frequency divider for frequency-dividing the signal frequency-divided by 2 n to generate a master index signal upon each rotation of said spindle motor; a time interval detector for detecting a time interval between the master index signal and the index signal output from said at least one magnetic disk unit and outputting a phase control signal and a select signal corresponding to the detected time interval; a data selector for selecting and outputting one of the signals frequency-divided by 2 1 , 2 2 , . . . , 2 N in accordance with the select signal; a clock window circuit for masking the master clock signal from said frequency generator for a time period in accordance with the phase control signal, the master index signal, and an output signal of said data selector; and a third frequency divider for frequency-dividing the output signal from said clock window circuit and supplying the frequency-divided signal as the clock signal to said at least one magnetic disk unit.

Claim 5

A spindle motor control system according to claim 2, wherein said clock window circuit comprises: a first flip-flop circuit (FF) for inputting the phase control signal as a clock signal; a second FF for inputting a Q output of said first FF as data and the master index signal as a clock signal; a third FF for inputting a Q output of said second FF; and a fourth FF for inputting a Q output of said third FF as data; and an AND gate for inputting Q output of said third FF and the master clock signal to output a gated clock signal to said third frequency divider; said third and fourth FFs inputting the output signal of said data selector as clock signals thereof, said second, third and fourth FFs being commonly cleared by the Q output of said first FF, and said first FF being cleared by a Q output of said fourth FF.

Claim 6

A spindle motor control system according to claim 1, wherein said time interval detector comprises: a first flip-flop circuit (FF) for inputting the master index signal and the index signal as data input and a clock, respectively; an AND circuit for ANDing a Q output of said first FF and the index signal to output the phase control signal to said clock window circuit; a second FF for inputting the phase control signal as a clock signal; a microprocessor for inputting a Q output of said second FF as a time interval signal and the phase control signal to output the select signal to said data selector; and a third FF for inputting a Q output of said second FF as an input data and the master index signal as a clock signal; the second FF being cleared by a Q output of said third FF.