Manufacturing process for a monolithic integrated semiconductor device having multiple epitaxial layers with a low concentration of impurities

Claim 1

A manufacturing process for a monolithic integrated semiconductor device comprising at least one power transistor and an integrated control circuit integrated on a single chip of semiconductor material, comprising the following steps: growing on a single crystal substrate a first epitaxial layer having a first type of conductivity, obtained by means of doping with a first dopant; doping the first epitaxial layer with a second dopant; forming a first region in said first epitaxial layer having a second type of conductivity opposite to the first type of conductivity; growing a second epitaxial layer having the first type of conductivity, obtained by doping with the first dopant, in such a way that said second epitaxial layer entirely covers the first epitaxial layer and the first region; forming at least a second region by doping the second epitaxial layer with a third dopant having the first type of conductivity, so that said second region is comprised within the first region; growing a third epitaxial layer having the first type of conductivity by doping with the first dopant so that said third epitaxial layer entirely covers the second epitaxial layer and the second region; forming at least one isolation region, having the second type of conductivity, that passes through the third and second epitaxial layers until it reaches the first region and delimits within it at least a first portion of the thrid and second epitaxial layers; forming within said first portion, delimited by the isolation region, elements of the integrated control circuit; forming one or more power transistors on the same chip; and forming electrodes on the front and back of the chip and metal interconnecting tracks among elements of the integrated control circuit and at least one power transistor on the front of the chip.