US4888680A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peripheral device interface and controller
Assignee: LITTLE BLUE LIIMITED PARTNERSHIP A OF CA LP
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Filing: 1987-10-14
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Granted: 1989-12-19
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Expires: 2007-10-14
Abstract
Abstract A port emulator circuit implemented on an Apple II peripheral card which enables MS-DOS programs designed to run on an 8086 microprocessor based IBM type personal computer to perform input/output operations on peripheral devices used by 6502 microprocessor based Apple II computers. As the 8086 requires I/O, a state machine, which forms part of the port emulator, performs the required bus arbitration between the 8086 and the 6502 and informs the 6502 of pending requirements of the 8086. The 6502 determines the type of I/O required, and using Apple II hardware resource, performs the I/O operation. The 6502 also places status information concerning the I/O operation in a portion of RAM on the peripheral card, which RAM location emulate the I/O registers found on IBM personal computers.
Inventors
- 👤 Wendell Sander
- 👤 Dick Huston
- 👤 Walter Broedner
- 👤 Clifford Huston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:36
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/387
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
212 words
An interfacing apparatus coupling first and second microprocessors which operate under first and second operating systems respectively to enable peripheral devices to be used for input/output operations in conjunction with the first microprocessor operating under the first operating system, to be used for input/output operations in conjunction with the second microprocessor operating under the second operating system, said first and second microprocessors having independent address buses, and data buses, said apparatus including said second microprocessor, a memory, a bus coupling said memory to and to a controller means, said controller means for controlling the input/output operations of said first and second microprocessors, said controller means comprising: control and instruction decode logic means coupled to said second microprocessor for decoding microinstructions generated by said second microprocessor and generating signals which allow the first microprocessor to control the second microprocessor; register means coupled to said memory and said control and instruction decode means, said register means for latching data on said buse for use by said control and instructions decode logic means; state machine means coupled to said register means, said control and instruction decode logic means and said second microprocessor for arbitrating the input/output accesses by the second microprocessor to be performed by the first processor using peripheral devices of said first microprocessor.
Claim 2
Dependent Claim
212 words
An interfacing apparatus coupling first and second microprocessors which operate under first and second operating systems respectively to enable peripheral devices to be used for input/output operations in conjunction with the first microprocessor operating under the first operating system, to be used for input/output operations in conjunction with the second microprocessor operating under the second operating system, said first and second microprocessors having independent address buses, and data buses, said apparatus including said second microprocessor, a memory, a bus coupling said memory to and to a controller means, said controller means for controlling the input/output operations of said first and second microprocessors, said controller means comprising: control and instruction decode logic means coupled to said second microprocessor for decoding microinstructions generated by said second microprocessor and generating signals which allow the first microprocessor to control the second microprocessor; register means coupled to said memory and said control and instruction decode means, said register means for latching data on said buse for use by said control and instructions decode logic means; state machine means coupled to said register means, said control and instruction decode logic means and said second microprocessor for arbitrating the input/output accesses by the second microprocessor to be performed by the first processor using peripheral devices of said first microprocessor.
Claim 3
Dependent Claim
54 words
The apparatus defined by claim 1 wherein said control and instruction decode logic means comprises means for reading input/output control bytes and data bytes in said memory, means for holding operation of said second microprocessor, said input/output control bytes containing the status of said corresponding input/output data bytes as determined by said first microprocessor.
Claim 4
Dependent Claim
86 words
The apparatus defined by claim 1 wherein said state machine comprises a state 0, a state 1, a state 2 and a state 3, and transitions between state 0, state 1, state 2 and state 3 occur on the following branch conditions: ______________________________________
Present Branch Next
State Condition State
______________________________________
0 /IOSTE 0
0 IOSTE*/BB*/BA
0
0 IOSTE*/BB*BA 3
0 IOSTE*BB l
1 PINT l
1 /PINT 2
2 /IRW*/IA 2
2 (IRW + IA)*/BA
0
2 (IRW*IA)*BA 3
3 PINT 3
3 /PINT 0
______________________________________
References Cited (Backward Citations)
US4443850A
Cited
US4648034A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-18 | 1993-06-19 | 1993-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-18 | 1997-06-19 | 1997-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-18 | 2001-06-19 | 2001-12-19 | $7700.00 | Window Closed / Lapsed |