US4887136A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device and the method for manufacturing the same
Assignee: Mitsubishi Electric Corp
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Filing: 1987-10-20
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Granted: 1989-12-12
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Expires: 2007-10-20
Abstract
Abstract A dynamic semiconductor memory device comprising a substrate having one trench including two capacitors for memory cell capacitances of two bits, and two elements such as transistors for reading, writing, and storing information represented by charge, arranged symmetrically at the central portion of the trench so as to correspond to the memory cells for two bits, and a field oxide film formed at the center of the trench on the bottom and on the side walls for separating the capacitors and elements.
Inventors
- 👤 Yoshio Matsuda
- 👤 Kazuyasu Fujishima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:38
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; Y; Y10; Y10S; Y10S257/00; Y10S257/911
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
235 words
A semiconductor memory device, comprising: a semiconductor substrate of a certain conductivity type and having a main surface, and a trench formed for providing a capacitance for storing charge representing information; an insulating layer formed on the side walls and the bottom surface of said trench, said insulating layer comprising a thick insulating portion for separation formed in the longitudinal direction and only in the center region of the bottom surface of said trench, whereby said bottom surface of the trench is separated into one lateral half and the other lateral half; one impurity doped region of an opposite conductivity type formed on the side wall and the bottom surface of one lateral half of said trench and below said insulating layer; the other impurity doped region of the opposite conductivity type formed on the side wall and on the bottom surface of the other lateral half of said trench and below said insulating layer, said one and the other impurity doped regions are separated by said insulating portion; and a U-shaped conductive layer formed on the side walls and across the bottom surface of said trench through said insulating layer, said one and the other impurity doped regions sharing said U-shaped conductive layer and including portions of said impurity doped regions on the bottom surface of said trench adjacent said thick insulating portion of said insulating layer together forming separate capacitors for storing charge.
Claim 2
Dependent Claim
235 words
A semiconductor memory device, comprising: a semiconductor substrate of a certain conductivity type and having a main surface, and a trench formed for providing a capacitance for storing charge representing information; an insulating layer formed on the side walls and the bottom surface of said trench, said insulating layer comprising a thick insulating portion for separation formed in the longitudinal direction and only in the center region of the bottom surface of said trench, whereby said bottom surface of the trench is separated into one lateral half and the other lateral half; one impurity doped region of an opposite conductivity type formed on the side wall and the bottom surface of one lateral half of said trench and below said insulating layer; the other impurity doped region of the opposite conductivity type formed on the side wall and on the bottom surface of the other lateral half of said trench and below said insulating layer, said one and the other impurity doped regions are separated by said insulating portion; and a U-shaped conductive layer formed on the side walls and across the bottom surface of said trench through said insulating layer, said one and the other impurity doped regions sharing said U-shaped conductive layer and including portions of said impurity doped regions on the bottom surface of said trench adjacent said thick insulating portion of said insulating layer together forming separate capacitors for storing charge.
Claim 3
Dependent Claim
35 words
A semiconductor memory device according to claim 1, further comprising semiconductor elements respectively formed adjacent to the ends of said one and the other impurity doped regions on the main surface of said semiconductor substrate.
Claim 4
Dependent Claim
18 words
A semiconductor memory device according to claim 1, wherein each said semiconductor element comprises a field effect device.
Claim 5
Dependent Claim
46 words
A semiconductor memory device according to claim 3, wherein said field effect device comprises an insulated gate, one electrode and the other electrode formed below said insulated gate with the spacing therebetween, said spacing between said one electrode and the other electrode forming a channel region.
Claim 6
Dependent Claim
34 words
A semiconductor memory device according to claim 4, wherein one of said one electrode and the other electrode is connected to one of said one impurity doped region and the other impurity doped region.
Claim 7
Dependent Claim
16 words
A semiconductor memory device according to claim 5, wherein said conductive layer comprises a polysilicon layer.
Claim 8
Dependent Claim
17 words
A semiconductor memory device according to claim 6, wherein said insulating layer comprises a field oxide film.
Claim 9
Dependent Claim
26 words
A semiconductor memory device according to claim 7, wherein said insulating layer comprises an inversion preventing region for preventing inversion formed below said field oxide film.
Claim 10
Dependent Claim
34 words
A semiconductor memory device according to claim 8, wherein said inversion preventing region has the same conductivity type as said semiconductor substrate and the impurity concentration thereof is higher than that of said substrate.
Claim 11
Dependent Claim
39 words
A semiconductor memory device according to claim 9, wherein said conductive layer has a surface facing the side walls and the bottom surface of said trench, and wherein an oxide film is deposited on the surface of said trench.
Claim 12
Dependent Claim
36 words
A semiconductor memory device according to claim 1, wherein said insulating layer further is formed on the main surface of said substrate and extends within the inner surface of said U-shaped conductive layer in said trench.
References Cited (Backward Citations)
JPS5812739A
Cited
JPS59117258A
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JPS6156442A
Cited
JPS6158266A
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JPS61136256A
Cited
JPS61187263A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-11 | 1993-06-12 | 1993-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-11 | 1997-06-12 | 1997-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-11 | 2001-06-12 | 2001-12-12 | $7700.00 | Window Closed / Lapsed |