US4887053A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High frequency VLSI oscillator
Assignee: Nokia Bell Labs
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Filing: 1988-11-07
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Granted: 1989-12-12
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Expires: 2008-11-07
Abstract
Abstract Maximum frequency range in a VLSI voltage controllable crystal oscillator is obtained with a two-stage amplifier with feedback across both stages. The first stage is implemented by an MOS transistor connected in source-follower configuration to minimize input capacitance, and the second stage is implemented by a bipolar transistor to provide the needed gain. A bidirectional voltage limiter connected to a crystal node limits the oscillations to a symmetrical waveform. The bias of an output buffer amplifier may be selectively shifted to maintain optimum duty cycle with the different triggering levels of diverse logic driven by the oscillator, and the bias may be dynamically driven by an analog signal to provide a duty cycle-modulated output.
Inventors
- 👤 David M. Embree
- 👤 Shawn M. Logan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:01
CPC Classifications
H; H03; H03B; H03B5/00; H03B5/30; H03B5/32; H03B5/36; H03B5/366; H03B5/368; H03B5/364; H03B2200/00; H03B2200/003; H03B2200/0034; H03B2200/006; H03B2200/0062; H03B2200/0064
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
71 words
An electronic oscillator comprising; a first amplifying stage having an MOS transistor connected in source follower configuration; a second amplifying stage having a bipolar transistor of opposite polarity from said MOS transistor connected to said first amplifying stage; and feedback means connected between the output of said second stage and the input of said first stage; the transconductance of said bipolar transistor being substantially greater than that of said MOS transistor.
Claim 2
Dependent Claim
71 words
An electronic oscillator comprising; a first amplifying stage having an MOS transistor connected in source follower configuration; a second amplifying stage having a bipolar transistor of opposite polarity from said MOS transistor connected to said first amplifying stage; and feedback means connected between the output of said second stage and the input of said first stage; the transconductance of said bipolar transistor being substantially greater than that of said MOS transistor.
Claim 3
Dependent Claim
19 words
An electronic oscillator, as in claim 1, wherein said second amplifying stage is also connected in source follower configuration.
Claim 4
Dependent Claim
21 words
An electronic oscillator, as in claim 1, wherein said MOS transistor and said bipolar transistor are on the same silicon chip.
Claim 5
Dependent Claim
50 words
An electronic oscillator, as in claim 1, further comprising a resonator node connected to said input of said MOS transistor for connection to a resonator to control the frequency of oscillation; and bidirectional voltage limiting means connected to said resonator node to provide waveform symmetry at said second amplifying stage.
Claim 6
Dependent Claim
52 words
An electronic oscillator, as in claim 4, further comprising buffer amplifier means capacitively coupled to at least one of said amplifying stages to provide an oscillator circuit output; said buffer amplifier means having its zero-signal bias point substantially at its threshold voltage to preserve the waveform symmetry at said oscillator circuit output.
Claim 7
Dependent Claim
35 words
An electronic oscillator, as in claim 5, further comprising bias varying means connected to said buffer amplifier means for varying the buffer amplifier bias to correspondingly vary the duty cycle of said oscillator circuit output.
Claim 8
Dependent Claim
39 words
An electronic oscillator, as in claim 6, wherein said bias varying means selectively alters said buffer amplifier to compensate for a change in duty cycle caused by a change in the desired triggering level at said oscillator circuit output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-11 | 1993-06-12 | 1993-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-11 | 1997-06-12 | 1997-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-11 | 2001-06-12 | 2001-12-12 | $7700.00 | Window Closed / Lapsed |