Insulated gate FET having a buried insulating barrier

Claim 1

An insulated gate field effect transistor device having means for significantly increasing punch-through voltage, comprising: a substrate of a first conductivity type; a source region of a second conductivity type formed in the substrate; a drain region of the second conductivity type formed in the substrate in spaced relation with the source region to define a channel region of predetermined thickness between the source and drain regions, the thickness of the channel region being between the substrate surface and the innermost plane within the substrate which is able to intersect the source and drain regions, said innermost plane is disposed in a direction extending from and generally parallel to said substrate surface; a gate dielectric and gate electrode structure on the substrate surface, operable to produce an electric field in the channel region when a voltage is applied thereto; and an insulating barrier buried in the substrate, said insulating barrier being substantially planar and disposed perpendicularly to said substrate surface, and having at least a portion extending into at least the majority of the channel thickness toward said substrate surface from below said innermost plane within said substrate, but not intersecting said substrate surface.