US4882708A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1988-01-19
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Granted: 1989-11-21
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Expires: 2008-01-19
Abstract
Abstract A precharge circuit is provided between bit lines, on the one hand, and a power source potential on the other. The precharge circuit is controlled to be conductive/nonconductive by a clear signal. A control unit is also provided, which controls a decoder when the clear signal is supplied so as to set all the word lines in a selective state. In a clear mode, writing circuits write the same data simultaneously into all of the memory cells.
Inventors
- 👤 Shigeyuki Hayakawa
- 👤 Mitsuo Isobe
- 👤 Takayuki Ohtani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:18
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
164 words
A semiconductor memory device for simultaneously writing same data into all memory cells by a writing circuit in a clear mode, said device comprising: a plurality of memory cells for storing data; bit lines for performing data transfer to and from the memory cells; a sense amplifier for amplifying the data read out from the memory cells onto the bit lines; a writing circuit for writing data into said memory cells via said bit lines; word lines for selecting said memory cells; a row decoder for selecting said word lines; a column decoder for selecting said bit lines; an address input circuit for supplying an address signal to the column decoder; load means provided between said bit lines and a potential source, said load means being set in an off-state by the supply of a memory clear signal; and control means for controlling said decoders when said memory clear signal is supplied so as to set all the word lines in a selective state.
Claim 2
Dependent Claim
164 words
A semiconductor memory device for simultaneously writing same data into all memory cells by a writing circuit in a clear mode, said device comprising: a plurality of memory cells for storing data; bit lines for performing data transfer to and from the memory cells; a sense amplifier for amplifying the data read out from the memory cells onto the bit lines; a writing circuit for writing data into said memory cells via said bit lines; word lines for selecting said memory cells; a row decoder for selecting said word lines; a column decoder for selecting said bit lines; an address input circuit for supplying an address signal to the column decoder; load means provided between said bit lines and a potential source, said load means being set in an off-state by the supply of a memory clear signal; and control means for controlling said decoders when said memory clear signal is supplied so as to set all the word lines in a selective state.
Claim 3
Dependent Claim
177 words
A semiconductor memory device for simultaneously writing same data into all memory cells by a writing circuit in a clear mode, said device comprising: a plurality of memory cells for storing data; bit lines for performing data transfer to and from the memory cells; sense amplifiers for amplifying the data read out from the memory cells onto the bit lines; writing circuits for writing data into said memory cells via said bit lines; grouped word lines, each of said word lines for selecting a memory cell in one of grouped memory cells; a row decoder for selecting a group of word lines; a column decoder for selecting said bit lines; an address input circuit for supplying an address signal to the column decoder; load means provided between said bit lines and a potential source, said load means being set in an off-state by the supply of a memory clear signal; and control means for setting said grouped word lines in a selective state for each group of said memory cell when said memory clear signal is supplied.
Claim 4
Dependent Claim
177 words
A semiconductor memory device for simultaneously writing same data into all memory cells by a writing circuit in a clear mode, said device comprising: a plurality of memory cells for storing data; bit lines for performing data transfer to and from the memory cells; sense amplifiers for amplifying the data read out from the memory cells onto the bit lines; writing circuits for writing data into said memory cells via said bit lines; grouped word lines, each of said word lines for selecting a memory cell in one of grouped memory cells; a row decoder for selecting a group of word lines; a column decoder for selecting said bit lines; an address input circuit for supplying an address signal to the column decoder; load means provided between said bit lines and a potential source, said load means being set in an off-state by the supply of a memory clear signal; and control means for setting said grouped word lines in a selective state for each group of said memory cell when said memory clear signal is supplied.
Claim 5
Dependent Claim
65 words
The semiconductor memory device according to claim 1, wherein each of said decoders includes first and second NAND gates, for NANDing address signals, a NOR gate for receiving the outputs of said first and second NAND gates, and a MOS transistor connected between the output of the second NAND gate and a reference potential, and being supplied at the gate with said memory clear signal.
Claim 6
Dependent Claim
34 words
The semiconductor memory device according to claim 1, wherein said load means includes a MOS transistor provided between said bit lines and said potential source, for receiving, at the gate, said memory clear signal.
Claim 7
Dependent Claim
28 words
The semiconductor memory device according to claim 1, wherein each of said memory cells is a dynamic memory cell which includes a capacitor and a MOS transfer gate.
Claim 8
Dependent Claim
56 words
The semiconductor memory device according to claim 1, wherein each of said memory cells is a static memory cell which includes a flip-flop made up of a pair of load elements and a pair of driving MOS transistors, and a MOS transistor used as a transfer gate and provided between said bit lines and the flip-flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-20 | 1993-05-22 | 1993-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-20 | 1997-05-22 | 1997-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-20 | 2001-05-22 | 2001-11-21 | $7700.00 | Window Closed / Lapsed |