US4881201A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: HITACHI Ltd and HITACHI MICROCOMPUTER ENGINEERING Ltd
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Filing: 1987-07-28
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Granted: 1989-11-14
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Expires: 2007-07-28
Abstract
Abstract A semiconductor integrated circuit device includes a semiconductor nonvolatile memory, a booster circuit which generates a high voltage required for writing the data into said semiconductor nonvolatile memory, and a control circuit. With the thus constructed device, however, various external control signals often fail to assume definite levels when the power source is closed. If an operation mode to be designated is erroneously determined to be a write operation mode due to obscure levels of the external control signals, then the write operation is executed erroneously. To prevent such an eronneous operation from developing when the power source is closed, provision is made of a power souce closure detector circuit and a suitable gate circuit. Owing to these circuits, the output of the booster circuit is prevented from being applied to the memory element from the time from when the power source circuit is closed up to the time when the read operation mode is designated by an external control signal.
Inventors
- 👤 Nobuyuki Sato
- 👤 Kazuaki Ujiie
- 👤 Masaaki Terasawa
- 👤 Shinji Nabetani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:55
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/22; G11C16/225; G11C16/10; G11C16/20; G11C16/30; G11C5/00; G11C5/14; G11C5/147; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
232 words
A semiconductor non-volatile memory used in a microcomputer including means for processing data comprising: a memory circuit which includes a memory element for storing data, wherein a voltage equal to greater than a predetermined voltage level is required to be applied to said memory element in order to change the state of data stored in said memory element; voltage generating means for forming an output voltage of a level different from that of a power source voltage, said output voltage being equal to or greater than the predetermined voltage level required to change the state of data stored in said memory element; means for forming an internal control signal that changes from a first level to a second level when the data of said memory element is to be changed in response to a control signal; control means coupled to said internal control signal forming means; and writing means coupled to said memory circuit, to said voltage generating means and to said control means, said writing means including means for changing the state of data stored in said memory element in response to the second level of the applied internal control signal, wherein said control means includes a power source closure detector circuit for forming an inhibiting signal which prevents an internal control signal being applied to said writing means from changing to the second level when said power source is closed.
Claim 2
Dependent Claim
232 words
A semiconductor non-volatile memory used in a microcomputer including means for processing data comprising: a memory circuit which includes a memory element for storing data, wherein a voltage equal to greater than a predetermined voltage level is required to be applied to said memory element in order to change the state of data stored in said memory element; voltage generating means for forming an output voltage of a level different from that of a power source voltage, said output voltage being equal to or greater than the predetermined voltage level required to change the state of data stored in said memory element; means for forming an internal control signal that changes from a first level to a second level when the data of said memory element is to be changed in response to a control signal; control means coupled to said internal control signal forming means; and writing means coupled to said memory circuit, to said voltage generating means and to said control means, said writing means including means for changing the state of data stored in said memory element in response to the second level of the applied internal control signal, wherein said control means includes a power source closure detector circuit for forming an inhibiting signal which prevents an internal control signal being applied to said writing means from changing to the second level when said power source is closed.
Claim 3
Dependent Claim
31 words
A semiconductor non-volatile memory used in a microcomputer according to claim 1, wherein said memory element is constructed so that data can be electrically erased or data can be electrically written.
Claim 4
Dependent Claim
40 words
A semiconductor non-volatile memory used in a microcomputer according to claim 2, wherein said power source closure detector circuit comprises a flip-flop circuit which assumes a first condition for forming said inhibiting signal when the power source circuit is closed.
Claim 5
Dependent Claim
36 words
A semiconductor non-volatile memory used in a microcomputer according to claim 3, wherein said flip-flop circuit is coupled to said means for forming an internal control signal, and wherein said flip-flop circuit assumes a second condition.
Claim 6
Dependent Claim
44 words
A semiconductor non-volatile memory used in a microcomputer according to claim 4, wherein said control means includes a gate circuit which is coupled to said flip-flop circuit and to said means which forms the internal control signal to be applied to said writing means.
Claim 7
Dependent Claim
43 words
A semiconductor non-volatile memory used in a microcomputer according to claim 5, wherein said voltage generating means includes a booster circuit which, upon receipt of periodic pulse signals, produces a voltage of a level greater than the level of said power source voltage.
References Cited (Backward Citations)
US4692904A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-13 | 1993-05-15 | 1993-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-13 | 1997-05-15 | 1997-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-13 | 2001-05-15 | 2001-11-14 | $7700.00 | Window Closed / Lapsed |