Switching-relieved low-loss three-level inverter

Claim 2

A three-level inverter, comprising: at least one inverter phase having a series arrangement of first, second, third and fourth antiparallel circuits, each antiparallel circuit including a semiconductor switching element and a bypass diode; a phase output formed by a junction point of said second and third antiparallel circuits; a d-c voltage source which supplies voltage to the phase; first and second switching-on relief chokes which couple said series arrangement to the positive and negative potentials of the d-c voltage source; first and second voltage divider capacitors coupled to be supplied by the d-c voltage source, with a junction point formed between said first and second voltage divider capacitors; a first decoupling diode coupled between said junction point between said first and second voltage divider capacitors and a junction point between said first and second antiparallel circuits; a second decoupling diode coupled between said junction point between said first and second voltage divider capacitors and a junction point between said third and fourth antiparallel circuits; and means for relieving the semiconductor switching elements during a switching-off process, said means for relieving including: a first series circuit having a first wiring diode and a first switching-off relief capacitor, which said first series circuit shunts said first antiparallel circuit; a second series circuit having a second wiring diode and a second switching-off relief capacitor, which said second series circuit shunts said fourth antiparallel circuit; a third series circuit having a first storage capacitor and a first d-c load, which said third series circuit is shunted across said first voltage divider capacitor; a fourth series circuit having a second storage capacitor and a second d-c load, which said fourth series circuit is shunted across said second voltage divider capacitor; a third wiring diode coupled between the junction point of the first wiring diode and the first switching-off relief capacitor and the junction point of the first storage capacitor and the first d-c load; and a fourth wiring diode coupled between the junction point of the second wiring diode and the second switching-off relief capacitor and the junction point of the second storage capacitor and the second d-c load.

Claim 3

The three-level inverter according to claim 1, wherein said inverter has multiple phases, with each said phase coupled to the same said third series circuit by one said third wiring diode for each phase, and each said phase coupled to the same said fourth series circuit by one said fourth wiring diode for each phase.

Claim 4

The three-level inverter according to claim 1, wherein said first and second d-c loads are ohmic resistors.

Claim 5

The three-level inverter according to claim 1, wherein said first and second d-c loads are energy feedback devices, each said feedback device having a switching diode, a storage inductance and a coupling diode, wherein said switching device and said storage inductance are coupled in series to one of said first and second storage capacitors.

Claim 6

The three-level inverter according to claim 1, further comprising means for relieving the semiconductor switching elements during a switching-off of the second and third antiparallel circuits, said relieving means including a fifth series circuit having a first supplemental wiring capacitor and a first supplemental wiring diode coupled in parallel, a sixth series circuit having a second supplemental wiring capacitor and a second supplemental wiring diode, and means for discharging said first and second supplemental wiring capacitors.

Claim 7

The three-level inverter according to claim 5, wherein said means for discharging the supplemental wiring capacitors are third and fourth d-c loads, said third d-c load being coupled between the junction point of the first supplemental wiring capacitor and the first supplemental wiring diode and the output of the inverter phase, said fourth d-c load being coupled between the junction point of the second supplemental wiring capacitor and the second supplemental wiring diode and the output of the inverter phase.

Claim 8

The three-level inverter according to claim 6, wherein the third and fourth d-c loads are ohmic resistors.

Claim 9

The three-level inverter according to claim 5, wherein said means for discharging the supplemental wiring capacitors is a third d-c load coupled between the junction point of the first supplemental wiring capacitor and the first supplemental wiring diode and the junction point of the second supplemental wiring capacitor and the second supplemental wiring diode.

Claim 10

The three-level inverter according to claim 8, wherein said third d-c load is an ohmic resistor.

Claim 11

The three-level inverter according to claim 8, wherein said third d-c load is an energy feedback device having: an isolation transformer with a primary winding and a secondary winding; a damping resistor which couples said primary winding to the junction point of the first supplemental wiring capacitor and the first supplemental wiring diode, said primary winding also being coupled to the junction point of the second supplemental wiring capacitor and the second supplemental wiring diode; a further coupling diode which couples the secondary winding to the positive potential of the d-c voltage source, the secondary winding also being coupled to the negative potential of the d-c voltage source.

Claim 12

A three-level inverter, comprising: at least one inverter phase having a series arrangement of first, second, third and fourth antiparallel circuits, each antiparallel circuit including a semiconductor switching element and a bypass diode; a phase output formed by a junction point of said second and third antiparallel circuits; a d-c voltage source which supplies voltage to the phase; first and second switching-on relief chokes which couple said series arrangement to the positive and negative potentials of the d-c voltage source; first and second voltage divider capacitors coupled to be supplied by the d-c voltage source, with a junction point formed between said first and second voltage divider capacitors; a first decoupling diode coupled between said junction point between said first and second voltage divider capacitors and a junction point between said first and second antiparallel circuits; a second decoupling diode coupled between said junction point between said first and second voltage divider capacitors and a junction point between said third and fourth antiparallel circuits; and means for relieving the semiconductor switching elements during a switching-off process, said means for relieving including: a first series circuit having a first wiring diode and a first switching-off relief capacitor, which said first series shunts said first decoupling diode; a second series circuit having a second wiring diode and a second switching-off relief capacitor, which said second series shunts said second decoupling diode; a third series circuit having a first storage capacitor and a first d-c load, which said third series circuit is shunted across said first voltage divider capacitor and said first switching-on relief choke; a fourth series circuit having a second storage capacitor and a second d-c load, which said fourth series circuit is shunted across said second voltage divider capacitor and said second switching-on relief choke; a third wiring diode coupled between the junction point of the first wiring diode and the first switching-off relief capacitor and the junction point of the first storage capacitor and the first d-c load; and a fourth wiring diode coupled between the junction point of the second wiring diode and the second switching-off relief capacitor and the junction point of the second storage capacitor and the second d-c load.

Claim 13

A three-level inverter, comprising: at least one inverter phase having a series arrangement of first, second, third and fourth antiparallel circuits, each antiparallel circuit including a semiconductor switching element and a bypass diode; a phase output formed by a junction point of said second and third antiparallel circuits; a d-c voltage source which supplies voltage to the phase; first and second switching-on relief chokes which couple said series arrangement to the positive and negative potentials of the d-c voltage source; first and second voltage divider capacitors coupled to be supplied by the d-c voltage source, with a junction point formed between said first and second voltage divider capacitors; a first decoupling diode coupled between said junction point between said first and second voltage divider capacitors and a junction point between said first and second antiparallel circuits; a second decoupling diode coupled between said junction point between said first and second voltage divider capacitors and a junction point between said third and fourth antiparallel circuits; and means for relieving the semiconductor switching elements during a switching-off process, said means for relieving including: a first series circuit having a first wiring diode and a first switching-off relief capacitor, which said first series shunts said first decoupling diode; a second series circuit having a second wiring diode and a second switching-off relief capacitor, which said second series shunts said second decoupling diode; a third series circuit having a first storage capacitor and a first d-c load, which said third series circuit is shunted across said first voltage divider capacitor and said first switching-on relief choke; a fourth series circuit having a second storage capacitor and a second d-c load, which said fourth series circuit is shunted across said second voltage divider capacitor and said second switching-on relief choke; a third wiring diode coupled between the junction point of the first wiring diode and the first switching-off relief capacitor and the junction point of the first storage capacitor and the first d-c load; and a fourth wiring diode coupled between the junction point of the second wiring diode and the second switching-off relief capacitor and the junction point of the second storage capacitor and the second d-c load.

Claim 14

The three-level inverter according to claim 11, wherein said inverter has multiple phases, with each said phase coupled to the same said third series circuit by one said third wiring diode for each phase, and each said phase coupled to the same said fourth series circuit by one said fourth wiring diode for each phase.

Claim 15

The three-level inverter according to claim 11, wherein the first and second d-c loads are ohmic resistors.

Claim 16

The three-level inverter according to claim 11 wherein said first and second d-c loads are energy feedback devices, each of which has a switching device, a storage inductance and a coupling diode wherein said switching device and said storage inductance are coupled in series with one of said first and second storage capacitors, the junction point between the switching element and the storage inductance being coupled via the coupling diode to one of the positive and the negative potentials of the d-c voltage source.