US4881027A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement comprising input circuits to find a power output sum for application in multi-phase electricity meters
Assignee: Siemens Building Technologies AG
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Filing: 1988-07-28
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Granted: 1989-11-14
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Expires: 2008-07-28
Abstract
Abstract A circuit arrangement for summing power outputs is disclosed. The circuit arrangement is especially useful in connection with a multi-phase electricity meter. The arrangement includes a plurality of input circuits connected in sequence, each of which has a current-to-voltage converter and a multiplier connected to the current-to-voltage converter. A voltage-to-frequency converter is connected at the output of each multiplier. Starting, at least with the second input circuit in the sequence, an adder is connected to the voltage-to-frequency converter by means of two inputs of the adder. Two other inputs of the adder are connected to two outputs of the preceding input circuit in the sequence. Illustratively, two outputs of each adder form two outputs of the corresponding input circuit. A ternary encoder followed by a ternary decoder may be located between the outputs of one input circuit and the adder of the succeeding input circuit. The two outputs of the adder in the last input circuit in the sequence are connected to the inputs of a forwards/backwards counter. Each of the two outputs of the forwards/backwards counter is connected to a mechanism such as a stepping motor which activates a display.
Inventors
- 👤 Andreas Joder
- 👤 Franz Renggli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:01
CPC Classifications
G; G01; G01R; G01R21/00; G01R21/127; G01R21/1271
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
262 words
A circuit arrangement for summing power outputs for use in a multi-phase electricity meter, said circuit arrangement comprising: a plurality of inputs circuits arranged in a sequence, each of said input circuits comprising an input converter, a multiplier connected to said input converter, and a voltage-to-frequency converter connected to said multiplier, starting at least with the second input circuit in said sequence, each of said input circuits comprising an adder having a first input means connected to the voltage-to-frequency converter of the corresponding input circuit, a second input means connected to an output of the preceding input circuit in said sequence, and an output which forms an output of the corresponding input circuit. wherein each voltage-to-frequency converter is provided with a first output for positive power and a second output for negative power, the first input means of each adder comprises first and second inputs, the second input means of each adder comprises first and second inputs, each adder has first and second outputs, one for positive power and one for negative power, said first and second outputs of each adder forming first and second outputs of the corresponding input circuit, said first and second outputs of each frequency converter being connected, starting at least with the second input circuit in said sequence, to the first and second inputs of the first input means of the corresponding adder, and said first and second inputs of the second input means of each adder being connected to a position power output and a negative power output of the preceding input circuit in said sequence.
Claim 2
Dependent Claim
262 words
A circuit arrangement for summing power outputs for use in a multi-phase electricity meter, said circuit arrangement comprising: a plurality of inputs circuits arranged in a sequence, each of said input circuits comprising an input converter, a multiplier connected to said input converter, and a voltage-to-frequency converter connected to said multiplier, starting at least with the second input circuit in said sequence, each of said input circuits comprising an adder having a first input means connected to the voltage-to-frequency converter of the corresponding input circuit, a second input means connected to an output of the preceding input circuit in said sequence, and an output which forms an output of the corresponding input circuit. wherein each voltage-to-frequency converter is provided with a first output for positive power and a second output for negative power, the first input means of each adder comprises first and second inputs, the second input means of each adder comprises first and second inputs, each adder has first and second outputs, one for positive power and one for negative power, said first and second outputs of each adder forming first and second outputs of the corresponding input circuit, said first and second outputs of each frequency converter being connected, starting at least with the second input circuit in said sequence, to the first and second inputs of the first input means of the corresponding adder, and said first and second inputs of the second input means of each adder being connected to a position power output and a negative power output of the preceding input circuit in said sequence.
Claim 3
Dependent Claim
72 words
The arrangement of claim 1 wherein said arrangement further comprises a ternary encoder connected to the outputs of at least one adder of an input circuit in said sequence and a ternary decoder connected to the outputs of the ternary encoder, the outputs of the ternary decoder being connected to the first and second inputs of the second input means of the adder in the next succeeding input circuit of said sequence.
Claim 4
Dependent Claim
79 words
The arrangement of one of claims 1 or 2 wherein, said first and second input means of each adder are provided with first and second synchronization means, respectively, for the time delayed synchronization of first and second pairs of input signals to said adder present at said first and second input means, respectively, said first and second synchronization means including gate means for the time serial combination of pulses comprising said first and second pairs of input signals, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-13 | 1993-05-15 | 1993-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-13 | 1997-05-15 | 1997-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-13 | 2001-05-15 | 2001-11-14 | $7700.00 | Window Closed / Lapsed |