High accuracy current source and high accuracy transconductance stage

Claim 2

A current source comprising: first, second, third and fourth transistors each having a base terminal and a series current path between an emitter and a collector terminal; said first and second transistors having their emitter and collector terminals connected in series between a first reference terminal and an output terminal; said third transistor having its base terminal connected to a second reference terminal and its emitter and collector terminals connected to said base terminals of said first and second transistors respectively; said fourth transistor having its base terminal connected to a third reference terminal and its emitter and collector terminals connected to said second transistor's base terminal and said output terminal respectively to provide a low impedance current path therebetween.

Claim 3

A current source according to claim 1, wherein said third and fourth bipolar transistors have alpha's of approximately one.

Claim 4

A current source comprising: a first and second transistor having their emitter-collector paths connected in series between a first reference terminal and an output terminal; and correction means connected to bases of said first and second transistors and said output terminal for adding current to said output terminal as a function of base current of said first and second transistors, and for sensing incremented current through said second transistor and adding said sensed incremented current to said output terminal to cancel the effect of said second transistor on the impedance of said output terminal.

Claim 5

A current source comprising: a first and second transistor having their emitter-collector paths connected in series between a first reference terminal and an output terminal; and correction means connected to bases of said first and second transistors and said output terminal for adding current to said output terminal as a function of base current of said first and second transistors, and for sensing incremented current through said second transistor and adding said sensed incremented current to said output terminal to cancel the effect of said second transistor on the impedance of said output terminal.

Claim 6

A current source according to claim 3, wherein said correction means includes a third transistor having its emitter-collector path connected between said bases of said first and second transistors and a fourth transistor having its emitter-collector path connected between said second transistor's base and said output terminal.

Claim 7

A current source according to claim 4, wherein said third and fourth bipolar transistors have alpha's of approximately one.

Claim 8

A current source comprising: a first current means connected to an output terminal for providing a first output current and a first output impedance at said output terminal; a second current means connected to said output terminal for providing a second output current smaller than said first output current and a second output impedance larger than said first output impedance at said output terminal; and means connecting said first and second current means for controlling said second output current as a function of said first output current and cancelling said first output impedance.

Claim 9

A current source comprising: a first current means connected to an output terminal for providing a first output current and a first output impedance at said output terminal; a second current means connected to said output terminal for providing a second output current smaller than said first output current and a second output impedance larger than said first output impedance at said output terminal; and means connecting said first and second current means for controlling said second output current as a function of said first output current and cancelling said first output impedance.

Claim 10

A current source according to claim 6, wherein said first current means includes first and second bipolar transistors having their emitter-collector paths connected in series between a first reference terminal and said output terminal.

Claim 11

A current source according to claim 7, wherein said connecting means connects said second current means between said output terminal and bases of said first and second transistors.

Claim 12

A current source according to claim 7, wherein said second current means and connecting means include a third transistor having its emitter-collector path connected between bases of said first and second transistors and a fourth transistor having its emitter-collector path connected between said second transistor's base and said output terminal.

Claim 13

A current source according to claim 9, wherein said third and fourth bipolar transistors have alpha's of approximately one.

Claim 14

In a current mirror including an input leg connected between a current input terminal and a first reference terminal and an output leg connected to said input leg and between a current output terminal and said first reference terminal providing an output current at said output terminal proportional to an input current at said input terminal, the improvement being said output leg which comprises: first and second transistors having their emitter-collector paths connected in series between said first reference terminal and said output terminal and correction means connected to bases of said first and second transistors, said output terminal and said input leg for adding current to said output terminal as a function of base current of said first and second transistors and adding incremental current to said output terminal to increase impedance of said output terminal.

Claim 15

In a current mirror including an input leg connected between a current input terminal and a first reference terminal and an output leg connected to said input leg and between a current output terminal and said first reference terminal providing an output current at said output terminal proportional to an input current at said input terminal, the improvement being said output leg which comprises: first and second transistors having their emitter-collector paths connected in series between said first reference terminal and said output terminal and correction means connected to bases of said first and second transistors, said output terminal and said input leg for adding current to said output terminal as a function of base current of said first and second transistors and adding incremental current to said output terminal to increase impedance of said output terminal.

Claim 16

A current mirror according to claim 11, wherein said correction means includes a third transistor having its emitter-collector path connected between said bases of said first and second transistors and its base connected to said input leg, and a fourth transistor having its emitter-collector path connected between said second transistor's base and said output terminal.

Claim 17

A current mirror according to claim 12, wherein said third and fourth bipolar transistors have alpha's of approximately one.

Claim 18

A current mirror according to claim 12, wherein said input leg includes: a fifth transistor having its emitter-collector path connected between said first reference and said input terminals; and, a sixth transistor having its emitter-collector path connected between a base of said fifth transistor and said input terminal and its base connected to said base of said third transistor and said input terminal.

Claim 19

In a current mirror including an input leg connected between a current input terminal and a first reference terminal and an output leg connected to said input leg and between a current output terminal and said first reference terminal providing an output current at said output terminal proportional to an input current at said input terminal, the improvement being said output leg which comprises: a first current means connected to said output terminal and said input leg for providing a first output current and a first output impedance at said output terminal; a second current means connected to said output terminal and said input leg for providing a second output current smaller than said first output current and a second output impedance larger than said first output impedance at said output terminal; and means connecting said first and second current means for controlling said second output current as a function of said first output current and cancelling said first output impedance.

Claim 20

In a current mirror including an input leg connected between a current input terminal and a first reference terminal and an output leg connected to said input leg and between a current output terminal and said first reference terminal providing an output current at said output terminal proportional to an input current at said input terminal, the improvement being said output leg which comprises: a first current means connected to said output terminal and said input leg for providing a first output current and a first output impedance at said output terminal; a second current means connected to said output terminal and said input leg for providing a second output current smaller than said first output current and a second output impedance larger than said first output impedance at said output terminal; and means connecting said first and second current means for controlling said second output current as a function of said first output current and cancelling said first output impedance.

Claim 21

A current mirror according to claim 15, wherein said first current means includes first and second bipolar transistors having their emitter-collector paths connected in series between said first reference terminal and said output terminal.

Claim 22

A current mirror according to claim 16, wherein said connecting means connects said second current means between said output terminal and bases of said first and second transistors.

Claim 23

A current mirror according to claim 16, wherein said second current means and connecting means include a third transistor having its emitter-collector path connected between bases of said first and second transistors and its base connected to said input leg, and a fourth transistor having its emitter-collector path connected between said second transistor's base and said output terminal.

Claim 24

A current mirror according to claim 18, wherein said input leg includes: a fifth transistor having its emitter-collector path connected between said first reference and said input terminal; and, a sixth transistor having its emitter-collector path connected between a base of said fifth transistor and said input terminal and its base connected to said base of said third transistor and said input terminal.

Claim 25

A differential current to single-ended current converter including first and second variable current sources having first and second current input terminals and first and second output terminals, respectively, and subtracting means for subtracting output current at said first output terminal from the current at said second output terminal, said first and second variable current source each comprising: first and second transistors having their emitter-collector paths connected in series between a first reference terminal and its output terminal; correction means connected to bases of said first and second transistors and its output terminal for adding current to its output terminal as a function of base current of said first and second transistors and adding incremental current to said output terminal to increase impedance level of its output terminal as a function of current at its output terminal; and its current input terminal being connected to said series connected first and second transistors.

Claim 26

A differential current to single-ended current converter including first and second variable current sources having first and second current input terminals and first and second output terminals, respectively, and subtracting means for subtracting output current at said first output terminal from the current at said second output terminal, said first and second variable current source each comprising: first and second transistors having their emitter-collector paths connected in series between a first reference terminal and its output terminal; correction means connected to bases of said first and second transistors and its output terminal for adding current to its output terminal as a function of base current of said first and second transistors and adding incremental current to said output terminal to increase impedance level of its output terminal as a function of current at its output terminal; and its current input terminal being connected to said series connected first and second transistors.

Claim 27

A current converter according to claim 20, wherein said correction means includes a third transistor having its emitter-collector path connected between said bases of said first and second transistors and a fourth transistor having its emitter-collector path connected between said second transistor's base and its output terminal.

Claim 28

A current converter according to claim 21, wherein said third and fourth bipolar transistors have alpha's of approximately one.

Claim 29

A current converter according to claim 20, wherein said subtracting means includes a current mirror having input and output legs connected to said first and second output terminals respectively, for providing a difference signal at said second terminal.

Claim 30

A differential current to single-ended current converter including first and second variable current sources having first and second current input terminals and first and second output terminals, respectively, and subtracting means for subtracting output current at said first output terminal from the current at said second output terminal, said first and second variable current source each comprising: a first current means connected to its output terminal for providing a first output current and a first output impedance at its output terminal; a second current means connected to its output terminal for providing a second output current smaller than said first output current and a second output impedance larger than said first output impedance at its output terminal; means connecting said first and second current means for controlling said second output current as a function of said first output current and cancelling said first output impedance; and its input terminal being connected to said first current means.

Claim 31

A differential current to single-ended current converter including first and second variable current sources having first and second current input terminals and first and second output terminals, respectively, and subtracting means for subtracting output current at said first output terminal from the current at said second output terminal, said first and second variable current source each comprising: a first current means connected to its output terminal for providing a first output current and a first output impedance at its output terminal; a second current means connected to its output terminal for providing a second output current smaller than said first output current and a second output impedance larger than said first output impedance at its output terminal; means connecting said first and second current means for controlling said second output current as a function of said first output current and cancelling said first output impedance; and its input terminal being connected to said first current means.

Claim 32

A current converter according to claim 24, wherein said first current means includes first and second bipolar transistors having their emitter-collector paths connected in series between a first reference terminal and its output terminal.

Claim 33

A current converter according to claim 25, wherein said connecting means connects said second current means between its output terminal and bases of said first and second transistors.

Claim 34

A current converter according to claim 25, wherein said connecting means senses incremented current through said second transistor and adds said sensed incremented current to said output terminal to cancel the effect of said second transistor on the impedance of said output terminal.

Claim 35

A current converter according to claim 24, wherein said subtracting means includes a current mirror having input and output legs connected to said first and second output terminals respectively for providing a difference signal at said second output terminal.

Claim 36

A differential current to single-ended current converter including first and second variable current sources having first and second current input terminals and first and second output terminals, respectively, and subtracting means for subtracting output current at said first output terminal from the current at said second output terminal, said first and second variable current source each comprising: first, second, third and fourth transistors each having a control terminal and a series current path between a first and second terminal; said first and second transistors having their first and second terminals connected in series between a first reference terminal and its output terminal; said third transistor having its control terminal connected to a second reference terminal and its first and second terminals connected between said control terminals of said first and second transistors; said fourth transistor having its control terminal connected to a third reference terminal and its first and second terminals connected between said second transistor's control terminal and its output terminal.

Claim 37

A differential current to single-ended current converter including first and second variable current sources having first and second current input terminals and first and second output terminals, respectively, and subtracting means for subtracting output current at said first output terminal from the current at said second output terminal, said first and second variable current source each comprising: first, second, third and fourth transistors each having a control terminal and a series current path between a first and second terminal; said first and second transistors having their first and second terminals connected in series between a first reference terminal and its output terminal; said third transistor having its control terminal connected to a second reference terminal and its first and second terminals connected between said control terminals of said first and second transistors; said fourth transistor having its control terminal connected to a third reference terminal and its first and second terminals connected between said second transistor's control terminal and its output terminal.

Claim 38

A current converter according to claim 29, wherein said transistors are bipolar transistors, and said control, first and second terminals are base, emitter and collector terminals, respectively for providing a difference signal at said second output terminal.

Claim 39

A current converter according to claim 29, wherein said subtracting means includes a current mirror having input and output legs connected to said first and second output terminals respectively for providing a difference signal at said first output terminal.

Claim 40

A current source comprising: a first and second transistor having their emitter-collector paths connected in series between a first reference terminal and an output terminal; and correction means connected to bases of said first and second transistors and said output terminal for sensing incremental current through said second transistor and for adding said sensed incremental current to said output terminal to increase impedance level of said output terminal.

Claim 41

A current source comprising: a first and second transistor having their emitter-collector paths connected in series between a first reference terminal and an output terminal; and correction means connected to bases of said first and second transistors and said output terminal for sensing incremental current through said second transistor and for adding said sensed incremental current to said output terminal to increase impedance level of said output terminal.

Claim 42

A current source according to claim 32, wherein said correction means includes a third transistor having its emitter-collector path connected between said bases of said first and second transistors and a fourth transistor having its emitter-collector path connected between said second transistor's base and said output terminal.

Claim 43

A current source according to claim 33, wherein said correction means adds said sensed incremented current to said output terminal to cancel the effect of said second transistor on the impedance of said output terminal.