US4878221A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Error-correcting decoder for rapidly dealing with buffer overflow
Assignee: NEC Corp
•
Filing: 1987-12-28
•
Granted: 1989-10-31
•
Expires: 2007-12-28
Abstract
Abstract For use in decoding received code symbols corresponding to original code symbols consisting of original information symbols and original redundancy symbols and comprising a sequential decode controller (45) responsive to the received code symbols for producing a sequence of presumed information symbols corresponding to the respective original information symbols, an encoder replica (46, 47) responsive to the presumed information symbols for producing presumed code symbols consisting of the presumed information symbols and presumed redundancy symbols corresponding to the respective original redundancy symbols, and a likelihood calculator (48) for calculating likelihoods which the presumed code symbols have relative to the respective received code symbols, a decoder comprises a position counter (61) for counting position counts for the respective presumed information symbols in the sequence and a modifier (81) for giving a predetermined value, such as zero, to the likelihoods calculated for the respective presumed redundancy symbols until the position counts reach a predetermined count after initialization of the position counter. The position counter is initialized on dealing with buffer overflow of at least one buffer used in the decoder, such as a buffer (41, 43) for the received code symbols. Preferably, the predetermined count is equal to the number of presumed information symbols held at a time in the encoder replica for use in producing each presumed redundancy symbol.
Inventors
- 👤 Michio Shimada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:16
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/37; H03M13/39; H03M13/03; H03M13/05
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
292 words
An error-correcting decoder for use as a counterpart of an error-correction encoder for encoding a sequence of original information symbols into a sequence of original code symbols by production of original redundancy symbols in accordance with a predetermined rule and by addition of said redundancy symbols to the respective information symbols to form the respective code symbols, said decoder including a sequential decode controller for executing a sequential decoding algorithm on an input sequence of received code symbols corresponding to the respective original code symbols to produce a local sequence of presumed information symbols, an encoder replica for encoding said local sequence into a replica output sequence of presumed code symbols by production of presumed redundancy symbols in accordance with said predetermined rule and by addition of said presumed redundancy symbols to the respective presumed information symbols to form the respective presumed code symbols, and a likelihood calculator responsive to said input and said replica output sequences for calculating likelihoods which said presumed code symbols have relative to the respective received code symbols, said likelihood calculator thereby producing a likelihood signal representative of said likelihoods, wherein the improvement comprises: a position counter coupled to said sequential decode controller for counting position counts for the respective presumed information symbols in said local sequence to produce a count signal representative of said position counts; modifying means responsive to said count signal for modifying said likelihood signal into a modified signal by giving a predetermined value to the likelihoods calculated for the respective presumed redundancy symbols until said position counts reach a predetermined count after initialization of said position counter; and supplying means for supplying said modified signal to said sequential decode controller to make said modified signal control execution of said sequential decoding algorithm.
Claim 2
Dependent Claim
292 words
An error-correcting decoder for use as a counterpart of an error-correction encoder for encoding a sequence of original information symbols into a sequence of original code symbols by production of original redundancy symbols in accordance with a predetermined rule and by addition of said redundancy symbols to the respective information symbols to form the respective code symbols, said decoder including a sequential decode controller for executing a sequential decoding algorithm on an input sequence of received code symbols corresponding to the respective original code symbols to produce a local sequence of presumed information symbols, an encoder replica for encoding said local sequence into a replica output sequence of presumed code symbols by production of presumed redundancy symbols in accordance with said predetermined rule and by addition of said presumed redundancy symbols to the respective presumed information symbols to form the respective presumed code symbols, and a likelihood calculator responsive to said input and said replica output sequences for calculating likelihoods which said presumed code symbols have relative to the respective received code symbols, said likelihood calculator thereby producing a likelihood signal representative of said likelihoods, wherein the improvement comprises: a position counter coupled to said sequential decode controller for counting position counts for the respective presumed information symbols in said local sequence to produce a count signal representative of said position counts; modifying means responsive to said count signal for modifying said likelihood signal into a modified signal by giving a predetermined value to the likelihoods calculated for the respective presumed redundancy symbols until said position counts reach a predetermined count after initialization of said position counter; and supplying means for supplying said modified signal to said sequential decode controller to make said modified signal control execution of said sequential decoding algorithm.
Claim 3
Dependent Claim
106 words
A decoder as claimed in claim 1, said encoder replica holding a predetermined number of the presumed information symbols of said local sequence at each time instant as replica information symbols and for successively producing said replica information symbols as a replica information sequence, said decoder further including buffer means for buffering said input sequence and said replica information sequence and being subject to buffer overflow, said buffer means being connected to said sequential decode controller to inform said sequential decode controller of said buffer overflow, wherein said sequential decode controller produces an initializing signal for initializing said position counter on dealing with said buffer overflow.
Claim 4
Dependent Claim
17 words
A decoder as claimed in claim 2, wherein said predetermined count is equal to said predetermined number.
Claim 5
Dependent Claim
34 words
A decoder as claimed in claim 3, the likelihoods calculated for the respective presumed redundancy symbols being variable between a positive and a negative integer, wherein said predetermined value is not greater than zero.
Claim 6
Dependent Claim
113 words
A decoder as claimed in claim 1, said encoder replica producing said presumed redundancy symbols as a presumed redundancy symbol sequence in said replica output sequence, said input sequence including a partial sequence of received redundancy symbols corresponding to the respective original redundancy symbols, wherein: said likelihood calculator comprises a partial calculator responsive to said partial sequence and said presumed redundancy symbol sequence for calculating redundancy symbol likelihoods which the presumed redundancy symbols of said presumed redundancy symbol sequence have relative to the respective received redundancy symbols; said modifying means giving said predetermined value to said redundancy symbol likelihoods until the position counts reach said predetermined count after initialization of said position counter.
Claim 7
Dependent Claim
149 words
A decoder as claimed in claim 5, said encoder replica producing the presumed information symbols of said local sequence as fresh information symbols one at a time and for successively producing said fresh information symbols as a fresh information symbol sequence in said replica output sequence, said input sequence including a remaining sequence of received information symbols corresponding to the respective original information symbols, wherein: said likelihood calculator comprises a remaining calculator responsive to said remaining sequence and said fresh information symbol sequence for calculating information symbol likelihoods which said fresh information symbols have relative to the respective received information symbols, said remaining calculator thereby producing a partial signal representative of said information symbol likelihoods as a part of said likelihood signal; said sequential decode controller executing said sequential decoding algorithm in response to said partial signal alone while said predetermined value is given to said redundancy symbol likelihoods.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-30 | 1993-05-01 | 1993-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-30 | 1997-05-01 | 1997-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-30 | 2001-05-01 | 2001-10-31 | $7700.00 | Window Closed / Lapsed |