Microcomputer having Z-flag capable of detecting coincidence at high speed

Claim 2

A microcomputer comprising: operation means receiving two input data for executing designated operations in sequence for the two input data, zero detection means coupled to the operation means for detecting that the result of each of the designated operations is zero, storing means coupled to the zero detection means for storing the result of zero detection, and control means coupled to the zero detection means and the storing means for controlling the storing means to indicate that the result of operation is not zero although the zero is detected by the zero detection means after a non-zero has been detected once by the zero detection means and stored in the storing means in the sequence of the designated operations.

Claim 3

A microcomputer as claimed in claim 1 wherein the operation means includes an arithmetic and logic circuit having a pair of inputs connected to receive the two input data, and an output of a plurality of bits coupled to the zero detection means.

Claim 4

A microcomputer as claimed in claim 2 wherein the zero detection means includes a NOR circuit receiving in parallel all the bits of output data of the operation means for generating a signal of a high level when all the bits of output data of the operation means are zero.

Claim 5

A microcomputer as claimed in claim 3 wherein the storing means includes a Z flag constituted of a flip-flop receiving an output of the control means.

Claim 6

A microcomputer as claimed in claim 4 wherein the control means includes an AND circuit receiving at its one input an output of the NOR circuit and at its other input an output of the Z flag, an output of the AND circuit being coupled to an input of the Z flag.

Claim 7

A microcomputer as claimed in claim 5 further including a multiplexor having a first input connected to the output of the AND circuit and a second input connected to receive a setting signal, an output of the multiplexor being connected to the input of the Z flag.

Claim 8

A microcomputer comprising: an arithmetic and logic unit having a pair of input connected to receive a pair of n-bit data and one output for generating a n-bit data of operation result, the arithmetic and logic unit being capable of comparing a pair of input data each exceeding n-bits by sequentially performing a comparison operation for each n-bit portion of the input data pair, a NOR circuit receiving the n-bit operation result from the arithmetic and logic unit for generating a signal of a high level when all the bits of the operation result are zero in each of the sequential comparison operations, an AND circuit having a first input connected to an output of the NOR circuit and a second input, a multiplexor having a first input connected to an output of the AND circuit and a second input connected to receive a setting signal for start of coincidence detection operation, and a Z flag having an input connected to an output of the multiplexor and an output connected to the second input of the AND circuit, whereby when the coincidence detection operation is started, the setting signal of a high level is applied through the multiplexor to the Z flag so as to set the Z flag, and at each time the comparison operation is executed by the arithmetic and logic unit, the output of the AND circuit is inputted through the multiplexor to the Z flag, so that when the result of the comparison operation is a non-zero, the Z-flag is reset by the NOR circuit, and thereafter, the reset condition of the Z-flag is maintained, although the zero is again detected by the NOR circuit in the sequence of comparison operations, with the result that the result of the coincidence detection operation can be judged from only the Z flag.

Claim 9

A microcomputer comprising: an arithmetic and logic unit having a pair of input connected to receive a pair of n-bit data and one output for generating a n-bit data of operation result, the arithmetic and logic unit being capable of comparing a pair of input data each exceeding n-bits by sequentially performing a comparison operation for each n-bit portion of the input data pair, a NOR circuit receiving the n-bit operation result from the arithmetic and logic unit for generating a signal of a high level when all the bits of the operation result are zero in each of the sequential comparison operations, an AND circuit having a first input connected to an output of the NOR circuit and a second input, a multiplexor having a first input connected to an output of the AND circuit and a second input connected to receive a setting signal for start of coincidence detection operation, and a Z flag having an input connected to an output of the multiplexor and an output connected to the second input of the AND circuit, whereby when the coincidence detection operation is started, the setting signal of a high level is applied through the multiplexor to the Z flag so as to set the Z flag, and at each time the comparison operation is executed by the arithmetic and logic unit, the output of the AND circuit is inputted through the multiplexor to the Z flag, so that when the result of the comparison operation is a non-zero, the Z-flag is reset by the NOR circuit, and thereafter, the reset condition of the Z-flag is maintained, although the zero is again detected by the NOR circuit in the sequence of comparison operations, with the result that the result of the coincidence detection operation can be judged from only the Z flag.