Class B variable gain control circuit

Claim 2

A gain control circuit having an input and an output, comprising: a bias source for providing first and second bias signals; reference means receiving said first and second bias signals for providing first and second reference voltages; circuit means coupled to the input of the circuit responsive to an applied input signal for providing a dynamic control voltage at an output; an input stage including circuit means responsive to said input signal and said dynamic control voltage for permitting the absolute magnitude of said input signal to exceed the magnitude of said first bias signal, said input stage coupled between said input and said reference means and being biased by said first reference voltage; and an output stage including circuit means responsive to said dynamic control voltage for providing an output signal at the output of the circuit the absolute magnitude of which may exceed the magnitude of said second bias signal, said output stage being coupled between said output and said reference means and being biased by said second reference voltage wherein the ratio of said output and input signals is proportional to the ratio of said second and first bias signals.

Claim 3

The gain control circuit of claim 1 wherein said circuit means of said input stage includes: a first transistor having a base coupled to said reference means, an emitter and a collector; and a second transistor having a base coupled to said emitter of said first transistor, an emitter coupled to said output of said circuit means for providing a dynamic control voltage and an collector coupled to said input of the circuit.

Claim 4

The gain control circuit of claim 2 wherein said input stage includes: a current mirror having an input coupled to said collector of said first transistor, an output coupled to said collector of said second transistor and a common terminal to which a first potential is supplied; and diode means coupled between said emitter of said first transistor and a terminal to which a second potential is supplied.

Claim 5

The gain control circuit of claim 3 wherein said circuit means of said output stage includes: a third transistor having a base coupled to said reference means, an emitter and a collector; and a fourth transistor having a base coupled to said emitter of said third transistor, an emitter coupled to said output of said circuit means for providing a dynamic control voltage and an collector coupled to said output of the circuit.

Claim 6

The gain control circuit of claim 4 wherein said output stage includes: a current mirror having an input coupled to said collector of said third transistor, an output coupled to said collector of said fourth transistor and a common terminal to which said first potential is supplied; and additional diode means coupled between said emitter of said third transistor and a terminal to which said second potential is supplied.

Claim 7

The gain control circuit of claim 5 wherein said bias source includes a first current source for providing said first bias signal and a second current source for providing said second bias signal.

Claim 8

The gain control circuit of claim 6 wherein said reference means includes. at least one diode means coupled between said first current source and said output of said circuit means for providing a dynamic control voltage; and at least one diode means coupled between said second current source and said output of said circuit means for providing a dynamic control voltage.

Claim 9

The gain control circuit of claim 1 wherein said circuit means of said output stage includes: a first transistor having a base coupled to said reference means, an emitter and a collector; and a second transistor having a base coupled to said emitter of said first transistor, an emitter coupled to said output of said circuit means for providing a dynamic control voltage and an collector coupled to the output of the circuit.

Claim 10

The gain control circuit of claim 8 wherein said output stage includes: a current mirror having an input coupled to said collector of said first transistor, an output coupled to said collector of said second transistor and a common terminal to which a first potential is supplied; and diode means coupled between said emitter of said first transistor and a terminal to which a second potential is supplied. PG,15

Claim 11

An integrated gain control circuit having an input and an output, comprising: a bias source for providing first and second bias signals; reference means receiving said first and second bias signals for providing first and second reference voltages; circuit means coupled to the input of the circuit responsive to an applied input signal for providing a dynamic control voltage at an output; an input stage including circuit means responsive to said input signal and said dynamic control voltage for permitting the absolute magnitude of said input signal to exceed the magnitude of said first bias signal, said input stage coupled between said input and said reference means and being biased by said first reference voltage; and an output stage including circuit means responsive to said dynamic control voltage for providing an output signal at the output of the circuit the absolute magnitude of which may exceed the magnitude of said second bias signal, said output stage being coupled between said output and said reference means and being biased by said second reference voltage wherein the ratio of said output and input signals is proportional to the ratio of said second and first bias signals.

Claim 12

An integrated gain control circuit having an input and an output, comprising: a bias source for providing first and second bias signals; reference means receiving said first and second bias signals for providing first and second reference voltages; circuit means coupled to the input of the circuit responsive to an applied input signal for providing a dynamic control voltage at an output; an input stage including circuit means responsive to said input signal and said dynamic control voltage for permitting the absolute magnitude of said input signal to exceed the magnitude of said first bias signal, said input stage coupled between said input and said reference means and being biased by said first reference voltage; and an output stage including circuit means responsive to said dynamic control voltage for providing an output signal at the output of the circuit the absolute magnitude of which may exceed the magnitude of said second bias signal, said output stage being coupled between said output and said reference means and being biased by said second reference voltage wherein the ratio of said output and input signals is proportional to the ratio of said second and first bias signals.

Claim 13

The gain control circuit of claim 10 wherein said circuit means of said input stage includes: a first transistor having a base coupled to said reference means, an emitter and a collector; and a second transistor having a base coupled to said emitter of said first transistor, an emitter coupled to said output of said circuit means for providing a dynamic control voltage and an collector coupled to said input of the circuit.

Claim 14

The gain control circuit of claim 11 wherein said input stage includes: a current mirror having an input coupled to said collector of said first transistor, an output coupled to said collector of said second transistor and a common terminal to which a first potential is supplied; and diode means coupled between said emitter of said first transistor and a terminal to which a second potential is supplied.

Claim 15

The gain control circuit of claim 12 wherein said circuit means of said output stage includes: a third transistor having a base coupled to said reference means, an emitter and a collector; and a fourth transistor having a base coupled to said emitter of said third transistor, an emitter coupled to said output of said circuit means for providing a dynamic control voltage and an collector coupled to said output of the circuit.

Claim 16

The gain control circuit of claim 13 wherein said output stage includes: a current mirror having an input coupled to said collector of said third transistor, an output coupled to said collector of said fourth transistor and a common terminal to which said first potential is supplied; and additional diode means coupled between said emitter of said third transistor and a terminal to which said second potential is supplied.

Claim 17

The gain control circuit of claim 14 wherein said bias source includes a first current source for providing said first bias signal and a second current source for providing said second bias signal.

Claim 18

The gain control circuit of claim 15 wherein said reference means includes'. at least one diode means coupled between said first current source and said output of said circuit means for providing a dynamic control voltage; and at least one diode means coupled between said second current source and said output of said circuit means for providing a dynamic control voltage.

Claim 19

The gain control circuit of claim 10 wherein said circuit means of said output stage includes: a first transistor having a base coupled to said reference means, an emitter and a collector; and a second transistor having a base coupled to said emitter of said first transistor, an emitter coupled to said output of circuit means for providing a dynamic control voltage and an collector coupled to the output of the circuit.

Claim 20

The gain control circuit of claim 17 wherein said output stage includes: a current mirror having an input coupled to said collector of said first transistor, an output coupled to said collector of said second transistor and a common terminal to which a first potential is supplied; and diode means coupled between said emitter of said first transistor and a terminal to which a second potential is supplied.