Three-part decoder circuit

Claim 1

An electrical circuit suitable for decoding a binary data stream that has been encoded in a sequential bitcell code format, the encoding resulting in an encoded signal waveform that carries clock information and data information, which electrical circuit comprises: (a) a separator means (1) for inputting the encoded signal waveform and separating the clock information and the data information, and (ii) for generating an output clock signal pulse train, and an output data signal pulse train; (b) a clock timer for inputting the clock signal pulse train and generating a clock parameter CP that is a measure of a time elapsed between a first and a second clock signal pulse, for each of a succession of bitcells; (c) a data timer for inputting the data signal pulse train, and the clock signal pulse train, and at the advent of the first clock signal pulse, generating a data parameter that is a measure of a time elapsed between the first clock signal pulse and a first data signal pulse, for each of a succession of bitcells; and (d) a comparer means for (i) inputting the clock parameter CP, (ii) inputting the data parameter, (iii) generating a parameter CP/2, and (iv) generating a decoded output signal, the decoded output signal being assigned a first valuation if the data parameter is less than CP/2, and a second valuation if the data parameter is greater than CP/2.