US4876645A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Diagnostic system
Assignee: Fujitsu Ltd
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Filing: 1987-03-16
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Granted: 1989-10-24
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Expires: 2007-03-16
Abstract
Abstract In a logic unit provided with a plurality of internal registers, an internal memory and a combinational circuit, such as an arithmetic unit, at least one of the plurality of internal registers is arranged to be scanned in and out. During diagnosis, when executing an instruction which makes reference to the internal memory, the register that can be scanned in and scanned out is used in place of the internal memory for diagnosing the combinational circuit.
Inventors
- 👤 Katsuhiko Shioya
- 👤 Tetsuhiko Ifuku
- 👤 Seiichi Inamasu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:19
CPC Classifications
F; F27; F27D; F27D21/00; F27D21/0021
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
169 words
A data processor logic unit diagnostic system, comprising: a logic unit; memory means, connectable via memory control means to said logic unit to establish a first data path between said logic unit and said memory means, for storing process data to be processed by said logic unit; register means, connectable via register control means to said logic unit to establish a second data path, distinct from said first data path, between said register means and said logic unit, for storing test data for testing said logic unit; said memory control means being responsive to memory means input/output control signals for connecting said first data path, said register control means being responsive to register means input/output control signals for connecting said second data path; and converting means for receiving input/output control signals for the memory means and passing said input/output control signals for the memory means as either said memory means input/output control signals or said register means input/output control signals in response to respective states of a test signal.
Claim 2
Dependent Claim
169 words
A data processor logic unit diagnostic system, comprising: a logic unit; memory means, connectable via memory control means to said logic unit to establish a first data path between said logic unit and said memory means, for storing process data to be processed by said logic unit; register means, connectable via register control means to said logic unit to establish a second data path, distinct from said first data path, between said register means and said logic unit, for storing test data for testing said logic unit; said memory control means being responsive to memory means input/output control signals for connecting said first data path, said register control means being responsive to register means input/output control signals for connecting said second data path; and converting means for receiving input/output control signals for the memory means and passing said input/output control signals for the memory means as either said memory means input/output control signals or said register means input/output control signals in response to respective states of a test signal.
Claim 3
Dependent Claim
183 words
A system as recited in claim 1, wherein said memory control means comprises: a memory input gate connected between said logic unit and said memory means; a memory output gate connected between said logic unit and said memory means; wherein said register control means comprises: a register input gate connected between said logic unit and said register means; a register output gate connected between said logic unit and said register means; and wherein said converting means comprises: a control circuit, connected to said memory input and output gates and said register input and output gates, and connected to receive register enable and select signals, memory enable and select signals, and the test signal, responding to the test signal to block the memory enable and select signals from reaching said memory input and output gates and applying the memory enable and select signals to said register input and output gates as the register enable and select signals to allow the transfer of the test data to said logic unit from said register means and output data from said logic unit to said register means.
Claim 4
Dependent Claim
31 words
A system as recited in claim 1, wherein said register means is loaded in parallel when a test signal is not received and serially loaded when a test signal is received.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-23 | 1993-04-24 | 1993-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-23 | 1997-04-24 | 1997-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-23 | 2001-04-24 | 2001-10-24 | $7700.00 | Window Closed / Lapsed |