US4876211A
Expired / Lapsed
US
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Method for fabricating varactor diodes using ion implanation
Assignee: Raytheon Co
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Filing: 1988-08-09
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Granted: 1989-10-24
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Expires: 2008-08-09
Abstract
Abstract A process for fabricating varactor diodes using ion implantation techniques is described herein. Three successive implanations of N-type ions into a GaAs semi-insulating substrate provide a deep N + type conductivity layer about 2-3 microns below the front major surface with concentration of at least 2×10 18 ions/cm 3 . A fourth implantation of N type ions forms an N type conductivity layer over the N + layer. An implanation of P type ions forms the P type conductivity layer over the N type conducitivity layer. A single rapid thermal anneal is performed on the substrate to remove damage to the crystal structure and to electrically activate the implants. The basic doped layered semiconductor structure is thereby produced using ion implantation. This ion implantation process provides a method for fabricating monolithic diode devices reliably and in mass quantities, which can be integrated with other monolithic devices.
Inventors
- 👤 Hilda Kanber
- 👤 James C. Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 03:57
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/64
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
170 words
A method for manufacturing semiconductor structures having varactor profiles having deep N + type conductivity layers including the steps of: providing a semi-insulating substrate of III-V semiconductor material having an essentially flat major surface; implanting first silicon ions through said major surface of said substrate at an energy level in the range of from about 5 to 7 MeV and of a dose of from about 1×10 14 to 1×10 15 ions/cm 2 ; implanting second silicon ions through said major surface of said substrate at an energy level less than the energy level of said first implanting step and in the range of from about 3 to 5 MeV and of a dose of from about 1×10 14 to 1×10 15 ions/cm 2 ; implanting sulfur ions through said major surface of said substrate at an energy level of from about 5 to 7 MeV and a dose of from about 1×10 14 to 1×10 15 ions/cm 2 , thereby providing a deeply buried N + type conductivity layer.
Claim 2
Independent Claim
170 words
A method for manufacturing semiconductor structures having varactor profiles having deep N + type conductivity layers including the steps of: providing a semi-insulating substrate of III-V semiconductor material having an essentially flat major surface; implanting first silicon ions through said major surface of said substrate at an energy level in the range of from about 5 to 7 MeV and of a dose of from about 1×10 14 to 1×10 15 ions/cm 2 ; implanting second silicon ions through said major surface of said substrate at an energy level less than the energy level of said first implanting step and in the range of from about 3 to 5 MeV and of a dose of from about 1×10 14 to 1×10 15 ions/cm 2 ; implanting sulfur ions through said major surface of said substrate at an energy level of from about 5 to 7 MeV and a dose of from about 1×10 14 to 1×10 15 ions/cm 2 , thereby providing a deeply buried N + type conductivity layer.
Claim 3
Dependent Claim
55 words
The method defined in claim 1 further including implanting silicon ions through said major surface of said substrate at an energy level of from about 350 to 500 Kev and doses of from about 6×10 12 to 1×10 13 ions/cm 2 to provide an N type conductivity layer adjacent said N + type conductivity layer.
Claim 4
Dependent Claim
62 words
The method defined in claim 2 further including implanting P type ions through said major surface of said substrate at an energy level of from about 15 to 30 KeV and a dose of from about 5×10 14 to about 5×10 15 ions/cm 2 to provide a P + type conductivity layer between said N type conductivity layer and said major surface.
Claim 5
Dependent Claim
47 words
The method defined in claim 3 further including annealing said substrate in a high purity gas at a predetermined elevated temperature and for a predetermined time sufficient to remove substantial amounts of ion implantation damage in said wafer and to electrically activate the N and P implants.
Claim 6
Dependent Claim
31 words
The method defined in claim 4 wherein said predetermined elevated temperature is in the range of from about 900-1050° C. and said predetermined time is from about 5 to 20 seconds.
Claim 7
Dependent Claim
20 words
The method defined in claim 5 wherein said predetermined elevated temperature and time are 950° C. and 10 seconds, respectively.
Claim 8
Dependent Claim
29 words
The method defined in claim 5 further including providing said substrate with contact metallization to said N + type conductivity layer and to said P + type conductivity layer.
Claim 9
Dependent Claim
48 words
The method defined in claim 5 further including etching away portions of said P + type conductivity layer, N type conductivity layer and N + type conductivity layer to form a mesa of semiconductor material composed of said P + , N and N + type conductivity layers.
Claim 10
Dependent Claim
31 words
The method defined in claim 8 further including the step of depositing contact metallization to said N + type conductivity layer and said P + type conductivity layer in spaced relationship.
Claim 11
Dependent Claim
27 words
The method defined in claim 9 further including the step of depositing a layer of nonconductive material over said contact metallization and said mesa of semiconductor material.
Claim 12
Independent Claim
286 words
A method for manufacturing semiconductor structures having varactor profiles, including the steps of: providing a semi-insulating semiconductor substrate having a flat major surface; performing at least three ion implantations through said flat major surface into said substrate to form a deeply buried N + type conductivity layer including: implanting first silicon ions into said substrate at an energy level of from about 5 to 6 MeV and a dose of from about 1×10 14 to 1×10 15 ions/cm 2 ; implanting second silicon ions into said substrate at an energy level less than the energy level of said first implanting step and in the range of from about 3 to 5 MeV and a dose of from about 1×10 13 to 1×10 15 ions/cm 2 ; implanting sulfur ions into said substrate at an energy level of from about 5 to 7 Mev and a dose of from about 1×10 14 to 1×10 15 ions/cm 2 ; implanting third silicon ions through said major surface into said substrate at an energy level of from about 350 to 500 KeV and a dose of from about 6×10 12 to 1×10 13 ions/cm 2 to form an N type conductivity layer adjacent said N + type conductivity layer; implanting beryllium ions through said major surface into said substrate at an energy level of from about 20-30 KeV and a dose of from about 5×10 14 to 5×10 15 ions/cm 2 to form a P + type conductivity layer between said major surface and N type conductivity layer; annealing said substrate in a high purity atmosphere at a predetermined elevated temperature for a predetermined period of time sufficient to remove substantial amounts of ion implantation damage in said substrate.
Claim 13
Independent Claim
286 words
A method for manufacturing semiconductor structures having varactor profiles, including the steps of: providing a semi-insulating semiconductor substrate having a flat major surface; performing at least three ion implantations through said flat major surface into said substrate to form a deeply buried N + type conductivity layer including: implanting first silicon ions into said substrate at an energy level of from about 5 to 6 MeV and a dose of from about 1×10 14 to 1×10 15 ions/cm 2 ; implanting second silicon ions into said substrate at an energy level less than the energy level of said first implanting step and in the range of from about 3 to 5 MeV and a dose of from about 1×10 13 to 1×10 15 ions/cm 2 ; implanting sulfur ions into said substrate at an energy level of from about 5 to 7 Mev and a dose of from about 1×10 14 to 1×10 15 ions/cm 2 ; implanting third silicon ions through said major surface into said substrate at an energy level of from about 350 to 500 KeV and a dose of from about 6×10 12 to 1×10 13 ions/cm 2 to form an N type conductivity layer adjacent said N + type conductivity layer; implanting beryllium ions through said major surface into said substrate at an energy level of from about 20-30 KeV and a dose of from about 5×10 14 to 5×10 15 ions/cm 2 to form a P + type conductivity layer between said major surface and N type conductivity layer; annealing said substrate in a high purity atmosphere at a predetermined elevated temperature for a predetermined period of time sufficient to remove substantial amounts of ion implantation damage in said substrate.
Claim 14
Dependent Claim
32 words
The method defined in claim 11 wherein said first silicon ions are implanted at an energy level of about 6 MeV and a dose greater than about 1×10 14 ions/cm 2 .
Claim 15
Dependent Claim
32 words
The method defined in claim 12 wherein said second silicon ions are implanted at an energy level of about 4 MeV and a dose greater than about 1×10 13 ions/cm 2 .
Claim 16
Dependent Claim
31 words
The method defined in claim 13 wherein said sulfur ions are implanted at an energy level of about 6 MeV and a dose greater than about 1×10 14 ions/cm 2 .
Claim 17
Dependent Claim
32 words
The method defined in claim 14 wherein said third silicon ions are implanted at an energy level of about 400 KeV and a dose greater than about 6×10 12 ions/cm 2 .
Claim 18
Dependent Claim
32 words
The method defined in claim 11 wherein said predetermined elevated temperature is in the range from about 900 to 1050° C. and said predetermined time is from about 5 to 20 sec.
Claim 19
Dependent Claim
31 words
The method defined in claim 16 further including providing said substrate with contact metallization to said N + type conductivity layer and said P + type conductivity layer in spaced relationship.
References Cited (Backward Citations)
US4106953A
Cited
JPS53144277A
Cited
JPS55156373A
Cited
US4438445A
Cited
JPH0531795A
Cited
JPH05313370A
Cited
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