US4876176A
Expired / Lapsed
US
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Method for fabricating quasi-monolithic integrated circuits
Assignee: Eaton Corp
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Filing: 1987-04-20
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Granted: 1989-10-24
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Expires: 2007-04-20
Abstract
Abstract Method for fabrication of quasi-monolithic microwave integrated circuits in which metals, oxides, and processes are selected to enable fabrication of the circuits by first producing many layers of metals and oxides in situ without removing the circuit from its environmental chamber. This reduces inclusion of contaminating chemical films and particles between the desired layers. Circuit elements are then defined by processing of the layers by photolithography and other processes from the top of the circuit downward. Lumped and distributed capacitors, resistors, inductors, transmission lines, and contacts for active devices are monolithically defined, with a reduced number of process steps.
Inventors
- 👤 Joseph A. Calviello
- 👤 Paul R. Bie
- 👤 Ronald J. Pomian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:00
CPC Classifications
G; G03; G03F; G03F7/00; H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/05
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
131 words
A method for producing a quasi-monolithic integrated circuit comprising the steps of: (a) enclosing a substrate in an environmentally isolated chamber; (b) producing over a substantial portion of a surface of the substrate at least five superimposed layers of metals and oxides, wherein said metals include at least one from the group tantalum, molybdenum, tungsten, and gold, and wherein said oxides include at least one from the group of oxides of tantalum, molybdenum, and tungsten; (c) removing the circuit from said chamber; (d) sequentially processing patterned areas of said layers substantially from the exposed top layer downward, to define and produce circuit elements forming a partially complete integrated circuit, by processes including photolithography; and (e) bonding active circuit elements to the partial circuit to complete the fabrication of the quasi-monolithic circuit.
Claim 2
Independent Claim
131 words
A method for producing a quasi-monolithic integrated circuit comprising the steps of: (a) enclosing a substrate in an environmentally isolated chamber; (b) producing over a substantial portion of a surface of the substrate at least five superimposed layers of metals and oxides, wherein said metals include at least one from the group tantalum, molybdenum, tungsten, and gold, and wherein said oxides include at least one from the group of oxides of tantalum, molybdenum, and tungsten; (c) removing the circuit from said chamber; (d) sequentially processing patterned areas of said layers substantially from the exposed top layer downward, to define and produce circuit elements forming a partially complete integrated circuit, by processes including photolithography; and (e) bonding active circuit elements to the partial circuit to complete the fabrication of the quasi-monolithic circuit.
Claim 3
Dependent Claim
30 words
A method as in claim 1 and wherein said step of producing superimposed layers of metals and oxides comprises producing layers which include compounds of Ta 2 O 5 ,.
Claim 4
Dependent Claim
30 words
A method as in claim 1 and wherein the order of producing the circuit elements of step D includes: (a) defining capacitors, (b) defining circuit conductors, and (c) defining resistors.
Claim 5
Dependent Claim
22 words
A method as in claim 3 and wherein said step of producing circuit elements comprises producing both distributed and lumped circuit elements.
Claim 6
Dependent Claim
17 words
A method as in claim 1 and wherein said integrated circuit comprises a substrate of SI GaAs.
Claim 7
Dependent Claim
79 words
A method as in claim 1 and wherein said circuit elements comprise a layered capacitor on SI GaAs substrate and said step of producing said layers comprises producing them by the following procedures: produce a first Ta layer; produce a first Au layer; sputter deposit a second Ta layer; sputter deposit Ta X O Y where X and Y are integers; sputter deposit a third Ta layer; sputter deposit a second Au layer; sputter deposit a fourth Ta layer.
Claim 8
Dependent Claim
33 words
A method as in claim 6 and wherein at least one of said steps of producing a first Ta layer and of producing a first Au layer comprises producing by an evaporation process.
Claim 9
Dependent Claim
33 words
A method as in claim 6 and wherein at least one of said steps of producing a first Ta layer and of producing a first Au layer comprises producing by a sputtering process.
Claim 10
Dependent Claim
133 words
A method as in claim 6 and wherein said step of sequentially processing patterned areas comprises defining a layered capacitor on SI GaAs substrate as follows: (i) photolithographically defining a first electrode for a capacitor in said second Au layer by the following procedures apply photoresist; photoprocess for a first mask; plasma etch said fourth Ta layer with CF 4 ; remove photoresist; plasma etch said second Au layer with ArO 2 ; and, (ii) photolithographically defining a second electrode in said first Au layer by the following procedures apply photoresist; photoprocess for a second mask; plasma etch said third Ta layer and said Ta X O Y layer and said second Ta layer with CF 4 ; remove photoresist; and plasma etch said first and second Au layers with ArO 2 .
References Cited (Backward Citations)
US4789645A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-23 | 1993-04-24 | 1993-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-23 | 1997-04-24 | 1997-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-23 | 2001-04-24 | 2001-10-24 | $7700.00 | Window Closed / Lapsed |