US4875087A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit device having strip line structure therein
Assignee: Fujitsu Ltd
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Filing: 1988-07-22
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Granted: 1989-10-17
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Expires: 2008-07-22
Abstract
Abstract An integrated circuit device including: at least one semiconductor chip (3) having a plurality of circuit elements; a package (21 to 24) enclosing the semiconductor chip with a hermetic seal; and a strip line unit (15-2, 11-1b, 11-2, 20 and 23:15-1, 11-1, 11-2, 11-3, 12-1 and 20) for connecting the circuit elements in the semiconductor chip to circuit outside of the package. The stripline unit having a microstrip line structure and a triplate strip line structure serial-connected to the microstrip line structure and connecting the outside circuits. The triplate strip line structure has a characteristic impedance equal to that of the microstrip line structure so that the strip line unit satisfies the required impedance matching. A center of the conductive layer strip line of the triplate strip line structure has a smaller width than that of a microstrip line of the microstrip line structure to have a predetermined impedance so that the triplate strip line structure has a same characteristic impedance as that of the microstrip line structure.
Inventors
- 👤 Akira Miyauchi
- 👤 Hiroshi Nishimoto
- 👤 Tadashi Okiyama
- 👤 Hiroo Kitasagami
- 👤 Masahiro Sugimoto
- 👤 Haruo Tamada
- 👤 Shinji Emori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:42
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/601; H01; H01P; H01P5/00; H01P5/02; H01P5/022; H01P5/028; H01P5/08; H10W44/20; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0237; H05K3/00; H05K3/30; H05K3/32; H05K3/325; H10W44/203; H10W44/209; H10W72/00; H10W72/50; H10W72/541; H10W72/5449; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
226 words
An integrated circuit device, comprising: a first insulation layer having top and bottom surfaces; a strip line layer formed on the top surface of said first insulation layer and having a first portion of a first width, a second portion of a second width smaller than said first width, and a third portion of a width greater than said second width; a second insulation layer formed on said second portion of said strip line layer; a semiconductor chip mounted on the top surface of said first insulation layer and electrically coupled to said strip line layer; a first conductive layer formed on the bottom surface of said first insulation layer; a second conductive layer formed on said second insulation layer; a wall portion formed on said second conductive layer; and a cap formed on said, wall portion, said cap, said wall portion, said second conductive layer and said second insulation layer forming a hermetically sealed cavity, said first portion of said strip line layer being hermetically sealed within said cavity and, with said first insulation layer and said first conductive layer, forming a microstrip line structure having a first characteristic impedance, and said first insulation layer, said second portion of said strip line layer and said second insulating layer forming a triplate strip line structure having a second characteristic impedance equal to said first characteristic impedance.
Claim 2
Dependent Claim
226 words
An integrated circuit device, comprising: a first insulation layer having top and bottom surfaces; a strip line layer formed on the top surface of said first insulation layer and having a first portion of a first width, a second portion of a second width smaller than said first width, and a third portion of a width greater than said second width; a second insulation layer formed on said second portion of said strip line layer; a semiconductor chip mounted on the top surface of said first insulation layer and electrically coupled to said strip line layer; a first conductive layer formed on the bottom surface of said first insulation layer; a second conductive layer formed on said second insulation layer; a wall portion formed on said second conductive layer; and a cap formed on said, wall portion, said cap, said wall portion, said second conductive layer and said second insulation layer forming a hermetically sealed cavity, said first portion of said strip line layer being hermetically sealed within said cavity and, with said first insulation layer and said first conductive layer, forming a microstrip line structure having a first characteristic impedance, and said first insulation layer, said second portion of said strip line layer and said second insulating layer forming a triplate strip line structure having a second characteristic impedance equal to said first characteristic impedance.
Claim 3
Dependent Claim
24 words
An integrated circuit device according to claim 1, wherein said strip line layer has a same thickness throughout said first, second and third portions.
Claim 4
Dependent Claim
27 words
An integrated circuit device according to claim 1, wherein a thickness of said first insulation layer is approximately equal to a thickness of said second insulation layer.
Claim 5
Dependent Claim
163 words
An integrated circuit device, comprising: a first insulation layer; a second insulation layer formed below said first insulation layer; a viahole formed through said first and second insulation layers; a third insulation layer formed below said second insulation layer; a semiconductor chip mounted on said first insulation layer; a first strip line layer of a first width formed on said first insulation layer and electrically connected to said semiconductor chip; a first ground layer formed between said first and second insulation layers; a second strip line layer of a second width smaller than said first width and formed between said second and third insulation layers; a second ground layer formed on said third insulation layer; and an electrically conductive member embedded in said viahole in a direction perpendicular to a plane of said first and second insulation layers, said electrical conductive member connecting said first strip line layer and said second strip line layer and being electrically isolated from said first ground layer.
Claim 6
Dependent Claim
163 words
An integrated circuit device, comprising: a first insulation layer; a second insulation layer formed below said first insulation layer; a viahole formed through said first and second insulation layers; a third insulation layer formed below said second insulation layer; a semiconductor chip mounted on said first insulation layer; a first strip line layer of a first width formed on said first insulation layer and electrically connected to said semiconductor chip; a first ground layer formed between said first and second insulation layers; a second strip line layer of a second width smaller than said first width and formed between said second and third insulation layers; a second ground layer formed on said third insulation layer; and an electrically conductive member embedded in said viahole in a direction perpendicular to a plane of said first and second insulation layers, said electrical conductive member connecting said first strip line layer and said second strip line layer and being electrically isolated from said first ground layer.
Claim 7
Dependent Claim
20 words
An integrated circuit according to claim 4, wherein said first and second strip line layers are substantially equal in thickness.
Claim 8
Dependent Claim
19 words
An integrated circuit according to claim 4, wherein said first, second and third insulation layers have substantially equal thicknesses.
Claim 9
Dependent Claim
124 words
An integrated circuit device, comprising: a semiconductor chip; cap means, having top and side walls, for hermetically sealing said semiconductor chip; and a triplate structure, comprising: a first insulation layer; a strip line layer of a predetermined length formed on said first insulation layer and having a first portion of a first width, a second portion of a second width smaller than said first width, and a third portion of a width wider than said second width, said strip line layer being coupled to said semiconductor chip, said strip line layer having equal characteristic impedances throughout its length; and a second insulation layer formed on said second portion of said strip line layer, forming a portion of said side walls of said cap means.
Claim 10
Dependent Claim
124 words
An integrated circuit device, comprising: a semiconductor chip; cap means, having top and side walls, for hermetically sealing said semiconductor chip; and a triplate structure, comprising: a first insulation layer; a strip line layer of a predetermined length formed on said first insulation layer and having a first portion of a first width, a second portion of a second width smaller than said first width, and a third portion of a width wider than said second width, said strip line layer being coupled to said semiconductor chip, said strip line layer having equal characteristic impedances throughout its length; and a second insulation layer formed on said second portion of said strip line layer, forming a portion of said side walls of said cap means.
References Cited (Backward Citations)
US4047132A
Cited
GB2007911A
Cited
US4259684A
Cited
US4276558A
Cited
US4498122A
Cited
EP0198621A2
Cited
GB2181300A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-16 | 1993-04-17 | 1993-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-16 | 1997-04-17 | 1997-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-16 | 2001-04-17 | 2001-10-17 | $7700.00 | Window Closed / Lapsed |