US4875044A
Expired / Lapsed
US
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Digital limiting circuit
Assignee: Sony Corp
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Filing: 1987-12-01
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Granted: 1989-10-17
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Expires: 2007-12-01
Abstract
Abstract A digital limiter limits the amplitude of a digital video signal by replacing input data that lies outside the range defined by lower and upper limit levels. Such data are replaced respectively with (1) an average value of (a) the data preceding the first data lying outside the range and (b) the upper or lower limit level data and (2) an average value of (a) the data following the last data lying outside the range and (b) the upper or lower limit level data. This enables a good soft-limit operation without compromising the linearity of the video signal.
Inventors
- 👤 Yoshiyuki Ohta
- 👤 Taku Kihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:44
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/20; H04N5/205; H04N5/208; H03; H03G; H03G11/00; H03G11/008
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
219 words
A digital limiting circuit for limiting an input digital signal with n+1 bits, where n is a positive integer, so that an output digital signal with n bits is generated, said limiting circuit comprising: an input terminal supplied with the input digital signal with n+1 bits; digital signal level detecting means supplied with the most significant bit and the second most significant bit of said input digital signal for detecting whether the level L of said input digital signal is within the range 2.sup.n ≦L<2.sup.n+1 +2.sup.n ; switching signal generating means supplied with the output of said signal level detecting means for generating a switching signal; digital signal converting means for converting said input digital signal with n+1 bits into a converted digital signal with n bits; modified signal generating means for generating a modified signal composed of a digital signal having an extreme value of an n bit digital signal and a digital signal having the average value of said extreme value and said converted digital signal, where said extreme value is the lowest or highest value or to be represented in said output signal; and selecting means controlled by said switching signal and for selecting said modified signal or said converted digital signal, whereby said output digital signal with n bits is obtained from said selecting means.
Claim 2
Dependent Claim
219 words
A digital limiting circuit for limiting an input digital signal with n+1 bits, where n is a positive integer, so that an output digital signal with n bits is generated, said limiting circuit comprising: an input terminal supplied with the input digital signal with n+1 bits; digital signal level detecting means supplied with the most significant bit and the second most significant bit of said input digital signal for detecting whether the level L of said input digital signal is within the range 2.sup.n ≦L<2.sup.n+1 +2.sup.n ; switching signal generating means supplied with the output of said signal level detecting means for generating a switching signal; digital signal converting means for converting said input digital signal with n+1 bits into a converted digital signal with n bits; modified signal generating means for generating a modified signal composed of a digital signal having an extreme value of an n bit digital signal and a digital signal having the average value of said extreme value and said converted digital signal, where said extreme value is the lowest or highest value or to be represented in said output signal; and selecting means controlled by said switching signal and for selecting said modified signal or said converted digital signal, whereby said output digital signal with n bits is obtained from said selecting means.
Claim 3
Dependent Claim
33 words
A digital limiting circuit according to claim 1, wherein said digital signal level detecting means includes an exclusive-OR gate means connected to receive the two most significant bits of said input digital signal.
Claim 4
Dependent Claim
35 words
A digital limiting circuit according to claim 1, wherein said digital signal converting means includes a bit selector for selecting n bits of said input digital signal except for the second most significant bit thereof.
Claim 5
Dependent Claim
86 words
A digital limiting circuit according to claim 3, wherein said modified signal generating means includes a first multiplier for multiplying said converted digital signal by 1/2, a first inverter for inverting said converted digital signal, a second multiplier for multiplying the output of said first inverter by 1/2, a second inverter for inverting the output of said second multiplier, and a selector for selecting one of the outputs of said first multiplier and said second inverter by the most significant bit of said input digital signal.
Claim 6
Dependent Claim
89 words
A digital limiting circuit according to claim 1, wherein said digital signal converting means includes a bit converter for converting a digital signal having the level between 2 n and 2 n+1 +2 n to said converted digital signal with n bits, for converting a digital signal having a level smaller than 2 n to a minimum value of the n bit digital signal, and for converting a digital signal having a level larger than 2 n+1 +2 n to a maximum value of the n bit digital signal.
Claim 7
Dependent Claim
33 words
A digital limiting circuit according to claim 5, wherein said modified signal generating means includes a digital low pass filter means supplied with said converted digital signal and for generating the modified signal.
Claim 8
Dependent Claim
86 words
A digital limiting circuit according to claim 6, wherein said digital low pass filter means includes first and second delay circuits, each of said delay circuits delaying an input signal by one clock period of said input digital signal, and adding means for adding the input signal of said first delay circuit, the input signal of said second delay circuit, and the output of said second delay circuit with a ratio of 1:2:1, whereby the modified signal is obtained at the output of said adding means.
References Cited (Backward Citations)
US4305063A
Cited
US4335372A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-16 | 1993-04-17 | 1993-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-16 | 1997-04-17 | 1997-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-16 | 2001-04-17 | 2001-10-17 | $7700.00 | Window Closed / Lapsed |