US4875018A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mirror circuit assembly
Assignee: Siemens AG
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Filing: 1987-09-18
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Granted: 1989-10-17
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Expires: 2007-09-18
Abstract
Abstract A current mirror circuit assembly includes a first current mirror circuit formed of an input transistor connected as a diode and a mirror transistor. The input transistor and the mirror transistor have gate terminals connected to one another and output circuits with output terminals. One of the output terminals of each of the input transistor and the mirror transistor are connected to a supply potential. A regulating transistor has an output circuit connected in series with the output circuit of the mirror transistor. A second current mirror circuit is formed of transistors with output circuits. Other transistors are controlled by the other of the output terminals of a respective one of the input transistor and the mirror transistor. One of the other transistors is fed back to the regulating transistor and the other transistors are connected to the output circuits of the transistors of the second current mirror circuit.
Inventors
- 👤 Dieter Draxelmayr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:20
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/262; H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/345
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
164 words
Current mirror circuit assembly, comprising a first current mirror circuit formed of a first input transistor connected as a diode and a first mirror transistor, said input transistor and said mirror transistor having gate terminals connected to one another and output circuits with output terminals, one of said output terminals of each of said input transistor and said mirror transistor being connected to a supply potential, a regulating transistor having an output circuit connected in series with said output circuit of said mirror transistor, a second current mirror circuit formed of respective second input and mirror transistors with respective output circuits, other transistors each having respective gates, each being controlled by another one of said output terminals of a respective one of said first input transistor and said first mirror transistor, one of said other transistors having a feedback connected to said regulating transistor, and said other transistors being connected to said output circuits of said second transistors of said second current mirror circuit.
Claim 2
Dependent Claim
164 words
Current mirror circuit assembly, comprising a first current mirror circuit formed of a first input transistor connected as a diode and a first mirror transistor, said input transistor and said mirror transistor having gate terminals connected to one another and output circuits with output terminals, one of said output terminals of each of said input transistor and said mirror transistor being connected to a supply potential, a regulating transistor having an output circuit connected in series with said output circuit of said mirror transistor, a second current mirror circuit formed of respective second input and mirror transistors with respective output circuits, other transistors each having respective gates, each being controlled by another one of said output terminals of a respective one of said first input transistor and said first mirror transistor, one of said other transistors having a feedback connected to said regulating transistor, and said other transistors being connected to said output circuits of said second transistors of said second current mirror circuit.
Claim 3
Dependent Claim
34 words
Current mirror according to claim 1, wherein said other transistors have output circuits with output terminals and one of said output terminals of each of said other transistors is connected to the supply potential.
Claim 4
Dependent Claim
38 words
Current mirror according to claim 1, wherein said transistors of said first current mirror and said other transistors are of one conduction type, and said transistors of said second current mirror circuit are of the other conduction type.
Claim 5
Dependent Claim
38 words
Current mirror according to claim 2, wherein said regulating transistor is controlled by an output terminal of one of said other transistors connected to said output circuit of said second mirror transistor of said second current mirror circuit.
Claim 6
Dependent Claim
21 words
Current mirror according to claim 4, including a third current mirror circuit connected in series with said second current mirror circuit.
Claim 7
Dependent Claim
99 words
Current mirror according to claim 5, wherein said third current mirror circuit is formed of respective third input and mirror transistors with respective output circuits, and including shutoff means having additional transistors of different conduction types with respective output circuits being connected in parallel with said output circuit of said other transistor having a feedback to said regulating transistor and being connected in series with said output circuit of the mirror transistor of at least one of said second and third current mirror circuits, said additional transistors having gate terminals being connected together and controlled to provide reciprocal shutoff.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-16 | 1993-04-17 | 1993-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-16 | 1997-04-17 | 1997-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-16 | 2001-04-17 | 2001-10-17 | $7700.00 | Window Closed / Lapsed |