Integrated digital signal processing circuit for performing cosine transformation

Claim 1

An integrated circuit for the digital processing of signals, performing a specific transformation of input signals representing a digital values x j so as to produce signals representing n coefficients F v of the form ##EQU2## wherein f(j,v) is a function of the indexes j and v, comprising: a signal transmission bus for unidirectionally transmitting a signal of p bits representing a digital value; switches spaced apart along the bus for letting the signals pass along the bus or for interrupting these signals, with any two adjacent switches along the bus being actuated in phase opposition, so as to divide the bus into sections, each bus section communicating alternately with a preceding section and a following section; computing operators are connected to certain sections of the bus and may receive successive data of p bits therefrom, for carrying out a computation on this data and sending resulting data over this bus section; buffer memories are connected to other bus sections so as to receive several successive data therefrom and send them over a bus in an order different from the order in which they were received; microprogrammed sequences for controlling each of said computation operator or said buffer memory.