Lateral surface superlattice having negative differential conductivity novel process for producing same

Claim 2

A lateral surface superlattice device which exhibits negative differential conductivity at ambient temperatures, said superlattice device comprising: a first layer, said first layer being a thin, uniform planar layer of a first type of semiconductive material having an upper surface, a lower surface and opposing ends; a second layer of a second type of semiconductive material exhibiting predetermined energy gaps between the conduction and valence bands of said first and second types of semiconductive materials; conducting channel means separating said first and second layers of dissimilar semiconductor materials; a conducting channel formed between said first and second semiconductor layers; gate means received and positioned within a central portion of said upper surface of said first layer and communicating with said channel means, said gate comprising an open Schottky metal grid defining a gate pattern having a plurality of spaced-apart apertures within said pattern, each of said apertures separated on all sides by a Schottky metal wall; a plurality of electronically created, multi-dimensional charge carrier confinement regions laterally disposed within said cap layer and defined by said the walls of each aperture in said grid, said electronically created confinement regions serving as quantum wells having a periodicity of less than 800 Å.

Claim 3

The device of claim 1 wherein said first and second types of semiconductor materials are selected from group II-VI semiconductor materials.

Claim 4

The device of claim 1 wherein said first and second types of semiconductor materials are selected from Group III-V semiconductor materials.

Claim 5

The device of claim 1 wherein said first layer of semiconductive material is comprised of a relatively thin, generally uniform layer of Ga x Al 1-x As and second layer is comprised of GaAs.

Claim 6

The device of claim 1 additionally comprising drain and source electrodes at opposite ends of the upper surface of the device, and gate contact means cooperating with said drain and source electrodes and the gate formed by the central portion of said first layer to provide a transistor.

Claim 7

The device of claim 4 additionally comprising drain and source electrodes at opposite ends of the upper surface of the device, and gate contact means cooperating with said drain and source electrodes and the gate formed by the central portion of said first layer to provide a transistor.

Claim 8

A lateral surface superlattice device which exhibits negative differential conductivity, said superlattice device comprising: a first layer, said layer being a thin, uniform planar layer of a first type of semiconductive material having an upper surface, a lower surface and opposing ends; a plurality of spaced apart pillars disposed in a two-dimensional pattern within a central portion of the upper surface of said first layer, said pillars extended above the upper surface of said first layer, channels formed by the interstices between said pillars, said channels filled with a Schottky metal, said metal covering the tops of said pillars so as to form a continuous Schottky metal surface over said central portion of said first semiconductor layer; a second layer of a second type of semiconductive material exhibiting predetermined energy gaps between the conduction and valence bands of said first and second types of semiconductive materials; conducting channel means separating said first and second layers of dissimilar semiconductor materials; said central portion of said upper layer serving to forming a plurality of electronically created quantum wells.

Claim 9

A lateral surface superlattice device which exhibits negative differential conductivity, said superlattice device comprising: a first layer, said layer being a thin, uniform planar layer of a first type of semiconductive material having an upper surface, a lower surface and opposing ends; a plurality of spaced apart pillars disposed in a two-dimensional pattern within a central portion of the upper surface of said first layer, said pillars extended above the upper surface of said first layer, channels formed by the interstices between said pillars, said channels filled with a Schottky metal, said metal covering the tops of said pillars so as to form a continuous Schottky metal surface over said central portion of said first semiconductor layer; a second layer of a second type of semiconductive material exhibiting predetermined energy gaps between the conduction and valence bands of said first and second types of semiconductive materials; conducting channel means separating said first and second layers of dissimilar semiconductor materials; said central portion of said upper layer serving to forming a plurality of electronically created quantum wells.

Claim 10

The device of claim 7 wherein said first and second types of semiconductor material are selected from group II-VI semiconductor materials.

Claim 11

The device of claim 7 wherein said first and second types of semiconductor material are selected from group III-V semiconductor materials.

Claim 12

The semiconductor device of claim 7 wherein said first layer of semiconductive material is comprised of a relatively thin, generally uniform layer of Ga x Al 1-x As and second layer is GaAs.

Claim 13

The device of claim 7 additionally comprising drain and source electrodes at opposite ends of the upper surface of the device, and gate contact means cooperating with said drain and source electrodes and the gate formed by the central portion of said first layer to provide a transistor.

Claim 14

The device of claim 10 additionally comprising drain and source electrodes at opposite ends of the upper surface of the device, and gate contact means cooperating with said drain and source electrodes and gate to provide a transistor.

Claim 15

The device of claim 7 wherein the periodicity of the spaces between said pillars is less than 800 Å.

Claim 16

The device of claim 11 wherein the periodicity of the spaces between said pillars is less than 800 Å.

Claim 17

The device of claim 12 wherein the periodicity of the spaces between said pillars is less than 800 Å.

Claim 18

A high electron mobility transistor having a lateral superlattice structured gate which exhibits negative differential conductivity, said transistor comprising: a first layer, said layer being a thin, uniform planar layer of a first type of semiconductive material having an upper surface, a lower surface and opposing ends; a plurality of spaced apart pillars disposed in a two-dimensional pattern within a central portion of the upper surface of said first layer, said pillars extended above the upper surface of said first layer, channels formed by the interstices between said pillars, said channels filled with a Schottky metal, said metal covering the tops of said pillars so as to form a continuous Schottky metal surface over said central portion of said first semiconductor layer; a second layer of a second type of semiconductive material exhibiting predetermined energy gaps between the conduction and valence bands of said first and second types of semiconductive materials; conducting channel means separating said first and second layers of dissimilar semiconductor materials; said central portion of said upper layer serving to forming a plurality of electronically created quantum wells; drain and source electrodes at opposite ends of the upper surface of the device, and gate contact means cooperating with said drain and source electrodes and the gate formed by the central portion of said first layer.

Claim 19

A high electron mobility transistor having a lateral superlattice structured gate which exhibits negative differential conductivity, said transistor comprising: a first layer, said layer being a thin, uniform planar layer of a first type of semiconductive material having an upper surface, a lower surface and opposing ends; a plurality of spaced apart pillars disposed in a two-dimensional pattern within a central portion of the upper surface of said first layer, said pillars extended above the upper surface of said first layer, channels formed by the interstices between said pillars, said channels filled with a Schottky metal, said metal covering the tops of said pillars so as to form a continuous Schottky metal surface over said central portion of said first semiconductor layer; a second layer of a second type of semiconductive material exhibiting predetermined energy gaps between the conduction and valence bands of said first and second types of semiconductive materials; conducting channel means separating said first and second layers of dissimilar semiconductor materials; said central portion of said upper layer serving to forming a plurality of electronically created quantum wells; drain and source electrodes at opposite ends of the upper surface of the device, and gate contact means cooperating with said drain and source electrodes and the gate formed by the central portion of said first layer.

Claim 20

The device of claim 16 wherein said first and second types of semiconductor material are selected from group II-VI semiconductor materials.

Claim 21

The device of claim 16 wherein said first and second types of semiconductor material are selected from group III-V semiconductor materials.

Claim 22

The semiconductor device of claim 16 wherein said first layer of semiconductive material is comprised of a relatively thin, generally uniform layer of Ga x Al 1-x As and second layer is GaAs.

Claim 23

The device of claim 16 wherein the periodicity of the spaces between said pillars is less than 800 Å.

Claim 24

The device of claim 19 wherein the periodicity of the spaces between said pillars is less than 800 Å.