Memory chip array with inverting and non-inverting address drivers

Claim 2

In a memory comprised of a plurality of substantially identical memory chips arranged in at least one row, a source of address signals, means coupling said address signals to a plurality of said memory chips, a source of control signals, and means coupling said control signals to said plurality of memory chips; the improvement wherein said memory has at least first and second groups of chips, each group including at least one memory chip, said means coupling said address signals comprising means coupling said address signals in relatively inverted form to the memory chips of said first and second groups of chips respectively, and said means coupling said control signals comprises means applying said control signals in the same sense to the chips of said and second groups, whereby noise signals originating in said address signals are cancelled out in said control signals.

Claim 3

In a memory system comprised of a plurality of semiconductor memory chips, said memory chips each having at least one control terminal and a plurality of address terminals, a source of address signals, a source of control signals, and a mounting arrangement for said chips and including a plurality of address lines connected between said source of address signals and separate terminals of each of said chips, and a control line connected between said source of control signals and the control terminal of each said chip; the improvement wherein said source of address signals comprises means providing first and second relatively inverted address signals, said plurality of memory chips comprising first and second groups of memory chips, said address lines including a first plurality of address lines connected to apply said first address signals to the memory chips of said first group of memory chips and a second plurality of address lines connected to apply said second address signals to the memory chips of said second group of memory chips, whereby interference signals on said first and second pluralities of address lines induce interference signals of opposite sense in said control line.

Claim 4

In a memory system comprised of a plurality of semiconductor memory chips, said memory chips each having at least one control terminal and a plurality of address terminals, a source of address signals, a source of control signals, and a mounting arrangement for said chips and including a plurality of address lines connected between said source of address signals and separate terminals of each of said chips, and a control line connected between said source of control signals and the control terminal of each said chip; the improvement wherein said source of address signals comprises means providing first and second relatively inverted address signals, said plurality of memory chips comprising first and second groups of memory chips, said address lines including a first plurality of address lines connected to apply said first address signals to the memory chips of said first group of memory chips and a second plurality of address lines connected to apply said second address signals to the memory chips of said second group of memory chips, whereby interference signals on said first and second pluralities of address lines induce interference signals of opposite sense in said control line.

Claim 5

The memory system of claim 2 wherein said first and second groups of memory chips are arranged in a common column, said control line extends in a straight line on said mounting arrangement adjacent and between said memory chips of said first and second groups, and corresponding address lines of said first and second pluralities of address lines are in line with one another and extend in straight lines adjacent said the memory chips of said first and groups of memory chips respectively.

Claim 6

The memory system of claim 3 wherein said memory chips are dynamic memory chips, and said control line is a row address strobe line.

Claim 7

The memory system of claim 3 wherein said memory chips are dynamic memory chips, and said control line is a column address strobe line.

Claim 8

The memory system of claim 3 wherein said memory chips are dynamic memory chips, and said control line is a write enable signal line.

Claim 9

The memory system of claim 3 wherein said memory chips comprise ZIP packages.

Claim 10

The memory system of claim 2 wherein said first and second groups of memory chips are arranged in separate parallel spaced apart columns, said control line extends in a straight line on said mounting arrangement adjacent the memory chips of said first and second second groups of memory chips, whereby the portion of said control line passing adjacent said first group of chips is not in alignment with the portion thereof passing adjacent said second group of memory chips, and corresponding address lines of said first and second pluralities of address lines are displaced from one another as they pass adjacent the memory chips of said first and second groups respectively.

Claim 11

The memory system of claim 8 wherein said memory chips are dynamic memory chips, and said control line is a row address strobe line.

Claim 12

The memory system of claim 8 wherein said memory chips are dynamic memory chips, and said control line is a column address strobe line.

Claim 13

The memory system of claim 8 wherein said memory chips are dynamic memory chips, and said control line is a write enable signal line.

Claim 14

The memory system of claim 8 wherein said memory chips comprise ZIP packages.